Semiconductor treatment technology and semiconductor device preparation method

Abstract

The invention discloses a semiconductor treatment technology. The semiconductor treatment technology includes the step of providing a substrate and carrying out oxidation and oxidation layer removing treatment on the substrate at least once, wherein the oxidation and oxidation layer removing treatment includes the first step of carrying out oxidation treatment on the surface of the substrate and forming an oxidation layer on the surface of the substrate, and the second step of removing the oxidation layer and exposing the substrate. The invention further provides a semiconductor device preparation method through the semiconductor treatment technology so as to improve the performance of an embedded silicon germanium device. Through the oxidation and oxidation layer removing treatment, defects on the surface of the substrate can be reduced or eliminated, so the surface of the substrate is smooth and is beneficial for the next procedure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor processing technology and a method for preparing a semiconductor device. Background technique [0002] The fabrication of large scale integrated circuits requires a supply of large numbers of transistor elements representing the main circuit elements used to design circuits. Among them, for complex circuits (such as microprocessors, storage chips, etc.), because CMOS technology has superior characteristics of operating speed, power consumption, and cost-effectiveness, CMOS (complementary metal oxide semiconductors, including P-channel transistors and N Trench transistor, namely PMOS and NOMS) technology is currently the most promising approach. Whether it is an N-channel transistor or a P-channel transistor, it includes a PN junction through a highly doped drain region and a source region and a reverse electrode disposed between the drain regi...

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Problems solved by technology

[0010] However, in actual operation, the formed e-SiGe will have dislocation defects, such as figure 2 Shown in the oval box ( figure 2 The middle black part represents silicon germanium material), which affects the performance of embedded silicon germanium devices

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