Sequential equivalent sampling circuit and method based on delay signals

Abstract

The invention provides a sequential equivalent sampling circuit and method based on delay signals. The sampling circuit and method are based on the time broadening principle, and a programmable delay line, a programmable delay chip, a level conversion chip, a highly stable crystal oscillator and an FPGA are used for achieving sampling clock signal delay. The phase-locked loop technology is used for performing phase locking on clock signals output by the highly stable crystal oscillator so as to reduce shaking of a clock; the FPGA is used for controlling the delay step length and the total delay of the programmable delay line and the programmable delay chip; mutual combination of coarse delay of the programmable delay line and fine delay of the programmable delay chip is used, high-precision and large-scale stepping delay is performed on sampling clock signals, the minimum delay step length is 10ps, and the total delay reaches 512ns. The sequential equivalent sampling circuit and method based on the delay signals can be widely applied to a sequential equivalent sampling system.

Description

technical field [0001] The invention relates to a sampling circuit and a sampling method, which is a high-precision and large-range step-delay signal generation circuit and method. The delay technology can be applied to periodic and high-speed measuring instruments, especially the sequential equivalent sampling technology The instrument can improve the delay accuracy, expand the total delay, and improve the measurement accuracy of the instrument. Background technique [0002] The step-delay signal generation circuit and method are widely used in sequential equivalent sampling systems. Current sampling methods are mainly divided into equivalent sampling and real-time sampling, and equivalent sampling is further divided into sequential equivalent sampling and random equivalent sampling. Sequential equivalent sampling has the advantages of simple principle and fast equivalent speed. The sampling points are in time order, which is easy to realize waveform recovery. [0003] At...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a sequential equivalent sampling circuit and sampling method based on a delay signal with a minimum delay step size of 10 ps and a total delay of 512 ns. The time delay step is small, the delay range of the coarse delay is large, and it has the characteristics of low cost, small delay step and long total delay, which can be applied in the sequential equivalent sampling system, which solves the problem There are technical problems that cannot take into account the minimum delay step size of fine delay and the total delay at the same time

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