Power Clamp for esd protection between power supply and ground with dual channel technology

Abstract

The invention relates to a Power Clamp for ESD protection between a power supply and the ground by adopting a dual-channel technology. The adopted technical scheme is that the Power Clamp comprises an RC-triggered detection circuit, wherein R1 and C form an ESD monitoring circuit placed between VDD and VSS, a phase inverter I is placed behind an RC monitoring circuit, the input end is connected with a Filter node, and the output end is connected with a phase inverter II. The output end of the phase inverter II is connected with the grid of a PMOS1, the grid of an NMOS1 is grounded, the leakage of the NMOS1 is connected with the leakage of the PMOS1 and then connected with the grid of a BIGFET, and the grid of the BIGFET is simultaneously grounded through a resistor R. The Power Clamp adopts the dual-channel technology, an RC time constant only needs 10-50ns, and the layout area of the Power Clamp can be greatly decreased.

Description

technical field [0001] The invention relates to a Power Clamp that can be used for ESD protection between a power supply and a ground in a 65nm semiconductor process, in particular to an area-saving power clamp triggered by a resistor and a capacitor (clamping circuit between a power supply and a ground). Background technique [0002] Semiconductor processing technology enables the production of extremely small transistors. These tiny transistors have thin oxide insulating layers that are easily damaged by static electricity. Therefore, special care is required when handling these semiconductor devices. [0003] Electrostatic discharge (ESD, Electron Static Discharge) is an instantaneous process in which a large amount of static charge is poured into the integrated circuit from the outside to the inside when the pins of an integrated circuit are floating. The whole process takes about 100ns to 1us. When the electrostatic discharge of the integrated circuit will generate hu...

AI Technical Summary

Problems solved by technology

[0006] For a general RC-triggered Power clamp, in order to achieve an effective discharge of the ESD current, the RC time constant needs to be designed to be 0.5us-1us. Such a large RC time constant requires relatively large capacitance and resistance. Therefore, when designing an integrated circuit layout, R and C require relatively large layout area, resulting in waste

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