NMOS transistor and formation method thereof, and SRAM memory cell circuit

Abstract

The invention relates to an NMOS transistor and a formation method thereof, and a static random access memory (SRAM) cell circuit. The NMOS transistor comprises a semiconductor substrate, a gate structure arranged at the bottom of the semiconductor substrate, a flank arranged at the side wall of the gate structure, a source region, a drain region, and a stretching stress layer arranged on the source region or the drain region, wherein the source region and the drain region are arranged in the semiconductor substrate at the two sides of the gate structure. Because the stretching stress layer is arranged on the source region or the drain region, tensile stress exerted on the channel region are uniform and asymmetrical, so that saturation source-leakage currents of the MOS transistor at different current directions are different. Moreover, the MOS transistor is used as a transmission transistor of the SRAM memory cell circuit, so that the writing margin of the SRAM memory unit is improved under the circumstances that the reading margin of the SRAM memory unit is not reduced and thus the reading-writing stability of the SRAM memory unit is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an NMOS transistor with asymmetric source / drain region stress and a forming method, and an SRAM memory unit circuit with high writing margin. Background technique [0002] Static Random Access Memory (SRAM), as a member of the memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia player) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the storage unit of the existing 6T structure SRAM memory, the storage unit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 and a fourth NMOS transistor N4. [0004] The first PMOS transistor P1, the second PMOS transistor P2...

AI Technical Summary

Problems solved by technology

[0010] However, as the process node of the CMOS process decreases, the operating voltage decreases, and random doping leads to an increase in threshold voltage variation, which poses challenges to the read stability of SRAM.

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