nmos transistor and its formation method, sram memory cell circuit

Abstract

An NMOS transistor and its forming method, and an SRAM memory unit circuit, the NMOS transistor includes: a semiconductor substrate, a gate structure located on the surface of the semiconductor substrate, side walls located on the side walls of the gate structure, located on the The source region and the drain region in the semiconductor substrate on both sides of the gate structure, and the tensile stress layer located on the source region or the drain region. Since the tensile stress layer is located on the source region or the drain region, the channel region is subjected to uneven and symmetrical tensile stress, so that the saturated source and drain currents of the NMOS transistor in different current directions are different. Using the NMOS transistor as the transfer transistor of the SRAM storage unit circuit, thereby improving the write margin of the SRAM storage unit without reducing the read margin of the SRAM storage unit, thereby improving the read-write stability of the SRAM storage unit .

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an NMOS transistor with asymmetric source / drain region stress and a forming method, and an SRAM memory unit circuit with high writing margin. Background technique [0002] As a member of memory, Static Random Access Memory (SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) ) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the storage unit of the existing 6T structure SRAM memory, the storage unit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 and a fourth NMOS transistor N4. [0004] The first PMOS transistor P1, the second PMOS transistor P2, ...

AI Technical Summary

Problems solved by technology

[0010] However, as the process node of the CMOS process decreases, the operating voltage decreases, and random doping leads to an increase in threshold voltage variation, which poses challenges to the read stability of SRAM.

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