Shallow trench isolation chemical-mechanical planarization method

Abstract

The invention discloses a shallow trench isolation chemical-mechanical planarization method which comprises the steps that hard mask layers are formed on a substrate; photoetching / etching is carried out on the hard mask layers to form hard mask patterns; the hard mask patterns serve as mask etching substrates to form shallow trenches; an isolation layer is deposited in the hard mask layers and the shallow trenches, wherein height differences exist among tops, in different areas, of the isolation layer; a conformal protective layer is formed on the isolation layer; chemical-mechanical planarization is carried out on the isolation layer and the protective layer until the hard mask layers are exposed. According to the shallow trench isolation chemical-mechanical planarization method, oxide locate in bottoms in shallow trench areas is prevented from being excessively removed by means of the protective layer additionally arranged on the top of the oxide, and therefore uniformity of step heights is effectively improved.

Description

technical field [0001] The invention relates to a semiconductor device manufacturing method, in particular to a shallow trench isolation chemical mechanical planarization method capable of improving step height uniformity. Background technique [0002] As the level of circuit integration is greatly improved, the spacing between various devices in the integrated circuit is gradually reduced, making parasitic effects, electromagnetic interference, etc. greatly hinder the improvement of device performance. In the previous large-scale process, a local field oxide layer was used between adjacent devices to provide isolation insulation. However, after the size of the device is reduced, the insulation performance of the oxide layer is reduced, and it is difficult to provide accurate patterns. Since the introduction of shallow trench isolation (STI) technology from the 0.25μm technology node, high-density isolation of devices has become possible. In addition, as technology nodes c...

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Problems solved by technology

[0004] However, with the continuous increase of the depth of the shallow trench, after HDP-CVD, the silicon oxide thickness difference between the shallow trench isolation region and the non-shallow trench isolation region (active region or active region) becomes larger and larger. The larger the size, the greater the challenge for the next step Shallow Trench Isolation Chemical Mechanical Planarization (STI CMP) process to control the uniformity inside the wafer chip

Due to the large silicon oxide thickness drop (such as ), in the STI CMP process, the CMP abrasive will not only polish and remove the oxide on the top or peak, but also remove the oxide on the bottom or valley, so that this thickness drop cannot be directly eliminated by the CMP process, and will Inherited until the end of the CMP process

This causes part of the silicon oxide in the shallow trench to be worn away, forming dishing defects, which degrades the electrical performance of the device and even reduces the yield.

[0005] All in all, in the current STI manufacturing method, the large silicon oxide thickness difference reduces the uniformity of CMP and causes device defects

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