Laterally diffused low on-resistance MOS devices

Abstract

The invention discloses a laterally diffused low on-resistance MOS device, comprising: a P-type well layer and an N-type lightly doped layer located in a P-type substrate layer, and a gate region is arranged above the gate oxide layer; At least two grooves are opened between the source region and the N-type lightly doped layer and on the upper part of the P-type well layer, and the etching depth of the groove near the source region is smaller than that of the groove near the N-type lightly doped layer The etch depth, and the etch depth of several grooves increases sequentially from the source region to the N-type lightly doped layer; the N-type lightly doped layer has a P-type lightly doped region, the P The lightly doped N-type region is located in the middle region of the N-type lightly doped layer in the horizontal direction, and the P-type lightly doped region is located in the middle region of the N-type lightly doped layer in the vertical direction. Through the above method, the present invention can improve the breakdown voltage, reduce the specific on-resistance of the device, improve the response time and frequency characteristics, optimize the overall performance, and reduce the volume.

Description

Technical field [0001] The invention relates to a MOS device, in particular to a lateral diffusion type low on-resistance MOS device. Background technique [0002] Metal oxide power MOS semiconductor devices, with the rapid development of the semiconductor industry, power electronics technology represented by high-power semiconductor devices have developed rapidly, and the application fields have been expanding, such as AC motor control and printer drive circuits. Among various power devices today, the laterally diffused MOS semiconductor device LDMOS has a high working voltage and a relatively simple process, so LDMOS has broad development prospects. In the design of LDMOS devices, breakdown voltage and on-resistance have always been the main goals that people pay attention to when designing such devices. The thickness of the epitaxial layer, the doping concentration, and the length of the drift region are the most important parameters of LDMOS. The breakdown voltage can be inc...

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Problems solved by technology

[0003] With the development of device miniaturization, the existing LDMOS design occupies a large layout area, which is not conducive to its integration with other functional devices to further reduce the volume and expand the application range. Therefore, how to design a device that can effectively reduce the current Some LDMOS occupy the surface area of ​​the silicon wafer and can further improve the performance of the device, becoming a technical obstacle

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