Method, system, and program for cache coherency control

Abstract

To be achieved in the present invention is a cache coherency control, wherein scalability of a shared-memory type multiprocessor system is improved, and cost-performance is improved by restraining the cost of hardware and software. In a system for controlling cache coherency of a multi-processor system wherein a plurality of processors comprising caches and TLBs share system memory, each of the processors comprises a TLB control unit further comprising: a TLB searching unit for executing TLB searching; and a coherency handler for executing registration information processing of the TLB, when no hit is obtained in the TLB searching and a TLB interruption is generated. The coherency handler comprises: a TLB replacement handler for executing a search of a page table of the system memory, and registration information replacement of the TLB; a TLB-mistake exception handling unit for handling a TLB-mistake interruption, which occurs when the TLB interruption is not caused by a page fault, but registration information that matches the address does not exist in the TLB; and a storage exception handling unit for handling a storage interruption, which occurs when registration information that matches the address exists in the TLB, but accessing authority is infringed.

Description

technical field [0001] The present invention relates to cache coherency control, and in particular to a method, system and program for controlling cache coherency of a shared memory multiprocessor. Background technique [0002] A multiprocessor system executes multiple tasks or processes (hereinafter referred to as "processes") simultaneously. Each of the plurality of processes generally has a virtual address space for use in executing the process. Locations in such a virtual address space contain addresses that map to physical addresses in system memory. It is not uncommon for a single space in system memory to be mapped to multiple virtual addresses in a multiprocessor. When each of multiple processes uses virtual addresses, these addresses are translated into physical addresses in system memory and, if no appropriate instructions or data exist in the processor's cache, are used to execute each process , they are fetched from system memory and stored in cache. [0003]...

AI Technical Summary

Problems solved by technology

VM-based shared memory technology handles cache coherency within the same process, but it cannot handle cache coherency between different processes

Specifically, since it is common for general-purpose OSes that support virtual addresses and use a copy-on-write technique to manage memory to map the same physical page to multiple processes, VM-based shared memory techniques are suitable for data Limited to guaranteeing that the application's data is not shared by different processes, and cannot enforce cache coherence transparent to the application

In other words, the necessity of explicitly indicating the data of the same virtual address space shared by multiple processors occurs, and in order to apply this technique to existing software, it is necessary to rewrite the application program, thus causing problems related to it. Additional software costs

Thus, VM-based shared memory technology cannot be applied to general-purpose computers, and the applicability of the technology is limited to specific uses and scientific computing that allow redesign of programs

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