UHF (Ultra High Frequency) multi-protocol RFID (Radio Frequency Identification) reader-writer baseband signal processing IP (Internet Protocol) core and working method thereof
A baseband signal processing, reader-writer technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of high cost, lack of portability, and inability to perform free cutting, etc., and achieve low cost, good scalability, and broad The effect of applying the foreground
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Embodiment 1
[0032] Such as figure 2 shown.
[0033] A UHF multi-protocol RFID reader baseband signal processing IP core, the IP core is written in verilog language, and has a modular design, and the IP core includes a bus interface, a register mapping unit, a sending logic module, a receiving logic module, and a CRC -5 generation logic module, CRC-16 generation and verification logic module, encoding module, decoding module and clock frequency division module;
[0034] The register mapping unit is connected to the bus interface through the register interface, the control register group and the status register group in the register mapping unit are respectively connected to the sending logic module and the receiving logic module, and the control register group is used to control the sending logic module and the receiving logic module. Receiving logic module, the state register group is used to represent the various states of the IP core in the working process; the sending logic module an...
Embodiment 2
[0041] Such as Figure 1-3 shown.
[0042] A UHF multi-protocol RFID reader baseband signal processing IP core described in Embodiment 1 is applied to a field programmable gate array (FPGA). figure 1 In the figure, the FPGA shown is configured with a UHF multi-protocol RFID reader baseband signal processing IP core and a specific CPU core and peripherals to form an SOC chip, thus becoming the baseband part of the UHF RFID system. The CPU core shown is 8. 16 or 32-bit open source core (such as OR1200 core) or authorized CPU core (such as 51 core, ARM core). The baseband signal provided by the IP core is connected to the radio frequency board to form a UHF RFID reading and writing system.
[0043] The working method of applying the IP core in a field programmable gate array (FPGA), including steps (1) to (10):
[0044] The IP core needs to add a bus interface when it is applied, and carry out the matching modification of the relevant bus with the application system. The speci...
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