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Vertical parasitic PNP transistor and manufacturing method thereof in germanium silicon heterojunction bipolar transistor (HBT) technology

A PNP triode, vertical parasitic technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of large device area, reduced device size, and large collector connection resistance, to reduce collector resistance, Improve performance and save area

Active Publication Date: 2015-04-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the device area is large and the connection resistance of the collector is large
Since the extraction of the collector electrode in the prior art is realized through another active region adjacent to the collector region, and the other active region and the collector region need to be isolated by STI or other field oxygen, such This greatly limits the further reduction of the device size

Method used

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  • Vertical parasitic PNP transistor and manufacturing method thereof in germanium silicon heterojunction bipolar transistor (HBT) technology
  • Vertical parasitic PNP transistor and manufacturing method thereof in germanium silicon heterojunction bipolar transistor (HBT) technology
  • Vertical parasitic PNP transistor and manufacturing method thereof in germanium silicon heterojunction bipolar transistor (HBT) technology

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Embodiment Construction

[0037] Such as figure 1 Shown is a schematic structural diagram of a vertical parasitic PNP transistor in the SiGe HBT process of the embodiment of the present invention. In the silicon germanium HBT process of the embodiment of the present invention, the vertical parasitic PNP transistor is formed on the silicon substrate, and the active region is isolated by the shallow trench field oxygen 1 .

[0038] The base region 3 of the PNP transistor is composed of an N-type ion implantation region formed in the active region. The process conditions of the N-type ion implantation in the base area are as follows: the implanted impurity is phosphorus or arsenic, the energy condition is 100Kev-300Kev, and the dose is 1e14cm -2 ~1e16cm -2 .

[0039] A groove in contact with the base region 3 is formed in the shallow groove field oxygen 1 on the peripheral side of the base region 3, and the shallow groove field oxygen 1 located in the groove is removed, and the The depth of the groove...

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Abstract

The invention discloses a vertical parasitic PNP transistor in a germanium silicon heterojunction bipolar transistor (HBT) technology. A groove contacted with a base region is formed in shallow groove field oxygen in the circumference of the base region, the depth of the groove is smaller than or equal to that of the base region, polycrystalline silicon mixed with N type impurities is filled in the groove, a outer base region is formed by the polycrystalline silicon mixed with N type impurities, the outer base region are contacted with the base region on the sides of the base region, metal is arranged on the outer base region, and the metal is contacted with a base electrode and leads the base electrode out. The invention further discloses a manufacturing method of the vertical PNP transistor in the germanium silicon HBT technology. The vertical PNP transistor in the germanium silicon HBT technology can be used as an output component in a high speed and high gain HBT circuit, and thus one more component choice is supplied for the circuit, the size of a component, the parasitic effect of the component and the collector resistance of the PNP transistor are effectively reduced, the performance of the component is improved, and production lost can be reduced due to the fact that according to the manufacturing method of the vertical PNP transistor in the germanium silicon HBT technology, no extra technological conditions are needed.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP transistor in a silicon-germanium HBT process, and also relates to a method for manufacturing a vertical parasitic PNP transistor in a silicon-germanium HBT process. Background technique [0002] In RF applications, higher and higher device characteristic frequencies are required. In BiCMOS process technology, NPN transistors, especially silicon germanium (SiGe) heterojunction transistors (HBT) or germanium silicon carbon heterojunction transistors (SiGeC HBT) are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a certain current gain coefficient and cut-off frequency. [0003] In the prior art, the output device...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/737H01L29/06H01L21/331
Inventor 陈帆王永成陈雄斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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