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Method for building multi-processor node system with multiple cache consistency domains

A multi-processor and consistent technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as system efficiency decline, performance loss, remote memory speed deterioration, etc., to improve system performance and reduce system topology. The effect of complexity

Active Publication Date: 2013-11-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With so many node controllers, the scale of interconnection between nodes is very large, and the topology between nodes becomes more and more complex; the speed of cross-node access to remote memory is significantly deteriorated, which in turn leads to a rapid decline in system efficiency and a huge loss in performance

Method used

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  • Method for building multi-processor node system with multiple cache consistency domains
  • Method for building multi-processor node system with multiple cache consistency domains
  • Method for building multi-processor node system with multiple cache consistency domains

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Embodiment

[0043] A multi-processor system with multiple nodes, for each node, a unified logical cache coherence domain is built inside its node controller to completely contain multiple physical caches consisting of several processors and the node controller that are isolated from each other Consistency domain; and its nodes can be directly connected through the node controller or connected through the node router (NR) to form a single cache consistency domain between nodes;

[0044] In addition, the first-level node controller of the above-mentioned system can be connected to the second-level node controller, and a unified logical cache coherence domain is constructed inside the second-level node controller to completely contain the isolation between several first-level node controllers and the Multiple physical cache coherence domains composed of secondary node controllers; connected directly or through node routers (NRs) through their secondary node controllers to form a single cache ...

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Abstract

The present invention provides a method for constructing a multi-processor node system with multiple cache coherence domains. In this system, the directory established in the node controller needs to contain processor domain information, which can be configured by configuring the node controller and processing The cache coherency domain attribute of each port connected to the device is obtained. The present invention enables one node controller to support multiple physical cache consistency domains in the node. Its purpose is to reduce the number of node controllers in a multiprocessor computer system, reduce the scale of interconnection between nodes, reduce the topology complexity of nodes, and improve system efficiency; at the same time, it can also solve the problem of the number of processor interconnection ports and the ability to support The very limited number of processor IDs in the domain creates performance bottlenecks for building large-scale CC-NUMA systems.

Description

technical field [0001] The invention relates to the field of computer applications, in particular to a method for constructing a multi-processor node system with multiple cache coherency domains. Background technique [0002] For a multiprocessor system, its multiple processors share the system memory space. At present, the connection mode between multiprocessors has changed from bus connection to point-to-point connection, and the memory has also changed from being connected to an external bridge chip of the processor to being directly connected to the processor. Due to changes in memory mounting methods, the distribution of memory in the system also changes, resulting in non-uniform memory access in multiprocessor systems. Therefore, most current multiprocessor systems are NUMA (Non-Uniform Memory Access - non- Uniform Memory Access) architecture system. [0003] The NUMA architecture multiprocessor system has the following three important characteristics: [0004] 1. A...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/167G06F12/0817
CPCG06F12/082G06F12/0822G06F12/0826G06F15/17368G06F2212/1016G06F2212/1048G06F2212/2542G06F2212/622
Inventor 王恩东胡雷钧陈继承张东公维锋张峰
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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