48*30 bit multiplier based on Booth algorithm

A multiplier and algorithm technology, which is applied in the field of multiplier pipeline design, can solve the problems of high cost and multiple hardware, and achieve the effects of saving cost, reducing hardware resource consumption, and shortening the clock cycle

Inactive Publication Date: 2013-03-27
张友能
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  • Abstract
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Problems solved by technology

But its disadvantage is that it consumes more hardware and costs more

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  • 48*30 bit multiplier based on Booth algorithm
  • 48*30 bit multiplier based on Booth algorithm
  • 48*30 bit multiplier based on Booth algorithm

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Embodiment Construction

[0021] The specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing:

[0022] The main design idea of ​​the 48x30-bit multiplier based on the Booth algorithm in this embodiment is to use the Radix-4Booth algorithm to generate partial products and perform pipeline addition operations on the partial products. The generation of partial products is only determined by the multiplier. According to the Booth algorithm, any Reasonably select the number of partial product generating circuits to improve the performance of the multiplier, at the cost of adding more partial product generating circuits and adder circuits.

[0023] refer to Figure 5 As shown, the 48x30-bit multiplier based on the Booth algorithm in this embodiment includes a Bit shift control module, a partial product generator, a pipeline accumulation controller and a partial product pipeline accumulator. in:

[0024] The bit shift control module is used to recei...

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Abstract

The invention discloses a 48*30 bit multiplier based on a Booth algorithm. The multiplier comprises a Bit displacement control mode, a partial product generator, a linear accumulation controller and a partial product linear accumulator. According to the invention, partial products are firstly generated by the multiplier and then accumulated and summed to realize the multiplying operation of 48*30 bits, wherein the partial products are generated by using a Radix-4Booth algorithm and are processed in a linear summing manner, so that the number of the partial products to be summed is reduced greatly. Therefore, a clock period required for realization of the multiplying operation is shortened, and the algorithms of multiplication with symbolic numbers and without symbolic numbers are unified. As a result, the traditional serial multiplier and the traditional parallel multiplier for processing the consumption of bandwidth and hardware resources are compromised. Consequently, the hardware resource consumption in design is lowered greatly and the cost is saved obviously on the basis that the multiplier with a high bit width satisfies the requirement of the bandwidth speed of system design.

Description

technical field [0001] The invention relates to a multiplier pipeline design in the technical field of high-speed and large-capacity communication, in particular to a 48x30-bit multiplier based on Booth algorithm. Background technique [0002] With the rapid development of 3G communication technology, TD-SCDMA technology (referred to as TD technology) has also been widely used. At present, TD technology requires each communication base station and its application network elements to realize high-precision clock and time synchronization. The previous NTP technology has been unable to meet the needs of high-precision time synchronization, so it turns to high-precision clock and time synchronization protocols, such as IEEE1588 protocol, to realize accurate time synchronization of each network node in the TD system. [0003] In the IEEE1588 protocol, its standard time format is a time counter of 80 bits. The high 48bits represent the second part of the time, and the low 32bits...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 张友能
Owner 张友能
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