Method for generating TSV (through-silicon via) interconnection oriented three-dimensional integrated circuit clock topology structure

Abstract

The invention discloses a method for generating TSV (through-silicon via) interconnection oriented three-dimensional integrated circuit clock topology structure, which comprises the following steps: inputting clock endpoints, a clock source, a buffer library and TSV information of a three-dimensional integrated circuit; circling a large-density area for the clock endpoints on each layer by using a classification algorithm, and establishing a subtree; mapping unclassified clock endpoints on all layers and root nodes of the clock tree established in each classified area to a 2D (two-dimensional) plane; finding the nearest neighbor node of each node by using a method of establishing the nearest neighbor graphs through tube decomposition, and carrying out pairing on the nodes so as to generate a father node according to a nearest distance principle; and determining whether unpaired nodes exist, if unpaired nodes do not exist, inserting the nodes into the buffer library and the TSV information from top to bottom so as to generate a three-dimensional clock topological structure. The method disclosed by the invention ensures the uniform distribution of TSV based on a clock endpoint density classification algorithm, and avoids the over-dense insertion of TSV, thereby increasing the manufacturability and the reliability to some extent.

Description

technical field [0001] The invention relates to the technical field of electronic design automation, in particular to a method for generating a three-dimensional integrated circuit clock topology for TSV interconnection. Background technique [0002] With the continuous reduction of integrated feature size, three-dimensional integrated circuit (3D IC) has become one of the effective technical solutions that continue to follow Moore's Law. The interconnection length can be effectively reduced by three-dimensional stacking, thereby reducing interconnection delay, power consumption, area and cost. At present, the research on 3D IC design automation tools is mainly to improve on the basis of traditional 2D IC design automation tools. The lack of real and efficient 3D IC design automation tools for TSV interconnection has become a major bottleneck restricting the development of 3D ICs, especially the lack of 3D Clock Tree Synthesis (3D CTS) tools. [0003] The problem model of ...

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Problems solved by technology

[0010] (4) Conversion rate restrictions;

Especially when the size of TSV cannot be scaled down with the size of logic devices, the influence of TSV mutual coupling will bring large logic delay, power consumption and timing errors

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