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Packaging element of semiconductor device

A package and semiconductor technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc. rate, the effect of increasing the contact area

Active Publication Date: 2013-02-13
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the performance of the package of the semiconductor device formed in the prior art is not stable, and it is prone to short circuit

Method used

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  • Packaging element of semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0033] Please refer to Figure 4 , the semiconductor device packaging method of the first embodiment of the present invention, comprising:

[0034] Step S201, providing a chip with a pad on its surface, a passivation layer is formed on the surface of the chip, and the passivation layer has an opening exposing part of the pad surface;

[0035] Step S202, forming a bump on the surface of the pad in the opening, the size of the bump is smaller than the size of the opening;

[0036] Step S203 , forming a solder ball covering the surface of the bump and covering the surface of the pad at the bottom of the opening.

[0037] Specifically, please refer to Figure 5-Figure 8 , Figure 5-Figure 8 A schematic cross-sectional structure showing the packaging process of the semiconductor device according to the first embodiment of the present invention.

[0038] Please refer to Figure 5 , provide a chip 300 with pads 301 on its surface, a passivation layer 303 is formed on the surface...

no. 2 example

[0060] Different from the first embodiment of the present invention, in the second embodiment of the present invention, an anti-diffusion layer is formed on the top surface and side surface of the bump to prevent copper atoms in the bump and solder balls from The interdiffusion of tin atoms affects the bonding strength of solder balls. Moreover, the surface of the anti-diffusion layer is also covered with a wetting layer to improve the bonding force between the anti-diffusion layer and the solder balls.

[0061] Please refer to Figure 8 , in the second embodiment of the present invention, the packaging method of the semiconductor device includes:

[0062] Step S401, providing a chip with a pad on its surface, a passivation layer is formed on the surface of the chip, and the passivation layer has an opening exposing part of the pad surface;

[0063] Step S402, forming a bump on the surface of the pad in the opening, the size of the bump is smaller than the size of the openin...

no. 3 example

[0091] Slightly different from the second embodiment of the present invention, the anti-diffusion layer not only covers the surface of the bump, but also covers the surface of the pad in the opening, forming a skirt structure, so that the solder ball can more easily cover the surface of the pad when forming a solder ball , to further increase the strength of the solder ball.

[0092] Please refer to Figure 13 , the semiconductor device packaging method of the third embodiment of the present invention, comprising:

[0093] Step S601, providing a chip with a pad on its surface, a passivation layer is formed on the surface of the chip, and the passivation layer has an opening exposing part of the pad surface;

[0094] Step S602, forming a bump on the surface of the pad in the opening, the size of the bump is smaller than the size of the opening;

[0095] Step S603, forming an anti-diffusion layer covering the surface of the bump and covering the surface of the pad at the botto...

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Abstract

Discloses is a packaging element of a semiconductor device. The packaging element comprises a chip, a passivation layer, salient points and solder balls. Pads and integrated circuits are arranged on the surface of the chip and electrically connected; the passivation layer is placed on the surface of the chip and provided with openings which expose part of the pads; the salient points are arranged on the surfaces of the pads, and the sizes of the salient points are smaller than those of the openings; and the solder balls cover the tops and side walls of the salient points and the bottoms of the openings. The packaging element of the semiconductor device is not easy to short circuit, high in bonding strength between the solder balls and the salient points and stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a package of semiconductor devices. Background technique [0002] Packaging refers to the process of enclosing a device or circuit into a protective enclosure. Packaging is very important for semiconductor chips, because semiconductor chips must be isolated from the outside world to prevent impurities in the air from corroding the circuits of semiconductor chips and causing electrical performance degradation. Moreover, the packaged semiconductor chip is also convenient for mounting and transportation. [0003] A packaging method for a semiconductor device in the prior art, including: [0004] Please refer to figure 1 , providing a chip 100, the surface of the chip 100 is formed with an integrated circuit and a pad 101 electrically connected to the integrated circuit; [0005] Please refer to figure 2 , forming a passivation layer 103 on the surface of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498
CPCH01L24/13H01L24/11H01L2224/11H01L2224/13H01L2924/00012
Inventor 林仲珉
Owner NANTONG FUJITSU MICROELECTRONICS
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