Method for manufacturing power semiconductor device back

Abstract

The invention discloses a method for manufacturing a power semiconductor device back and aims to solve the problems of low impurity activation rate in the conventional process. The method for manufacturing the power semiconductor device back at least comprises the following steps of: thinning a silicon chip of which the front-side structure is completely processed; performing lattice pre-damage processing on the back of the silicon chip; performing ion implantation doping; performing impurity push processing at the temperature below 550 DEG C; and finishing lattice repair processing by laser annealing, wherein the method for performing lattice pre-damage processing comprises the following step of performing ion implantation on the back of the silicon chip according to the implantation concentration between 1015 and 1016; and the ions used for the ion implantation of the lattice pre-damage processing are silicon ion, germanium ion or hydrogen ion. According to the method for manufacturing the power semiconductor device back, an enhanced diffusion effect generated by ion implantation damage is utilized, the ion implantation impurities are effectively pushed and activated through the combination of the ion implantation lattice pre-damage processing, low-temperature push and laser annealing, and the method for manufacturing the power semiconductor device back is suitable for production and manufacture of multiple power devices.

Description

technical field [0001] The invention relates to a backside manufacturing process of a power semiconductor device. Background technique [0002] In the manufacturing process of power semiconductor devices, the silicon wafer is usually thinned to a certain thickness after the structure on the front side of the silicon wafer is processed, and the backside structure is realized by ion implantation doping and annealing from the backside of the silicon wafer. Since the melting point of metal aluminum on the front side of the silicon wafer is only 600°C, the conventional heat treatment temperature on the backside is below 550°C. At this temperature, the activation rate of ion implanted impurities is very low, generally not exceeding 30%, and the diffusion coefficient of conventional impurities at this temperature is also very low, and the advancement of impurities is very limited. SUMMARY OF THE INVENTION [0003] In order to overcome the above-mentioned drawbacks, the present i...

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Problems solved by technology

The activation rate of ion-implanted impurities at this temperature is very low, generally no more than 30%. At the same time, the diffusion coefficient of conventional impurities at this temperature is also very low, and the advancement of impurities is very limited.

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