soi MOS transistor

Abstract

The invention provides an SOI MOS transistor, comprising an active region formed in an SOI layer of an SOI substrate; a gate covering part of the active region; a source region and a drain region respectively located on both sides of the gate length direction In the active region, the width of the part of the source region and the drain region bordering the gate is equal; the part of the active region covered by the gate includes the width of the part of the source region and the drain region bordering the gate in the source region A channel region extending between the region and the drain region, wherein the active region includes at least two comb-shaped protrusions arranged at a certain interval in the length direction of the channel region on one side of the channel region in the width direction or both sides; wherein, the part of the end of the comb-shaped protrusion not covered by the gate is the body contact region. The SOI MOS transistor provided by the invention can reduce lateral leakage, body resistance and parasitic capacitance.

Description

technical field [0001] The present invention relates to the field of semiconductor transistors, in particular to a SOI MOS transistor for suppressing the floating body effect of SOI MOS (Metal Oxide Semiconductor) transistors. Background technique [0002] SOI (Silicon On Insulator) refers to silicon-on-insulator technology, and SOI technology is recognized as one of the mainstream semiconductor technologies in the 21st century. SOI technology effectively overcomes the insufficiency of bulk silicon materials and fully utilizes the potential of silicon integrated circuit technology. [0003] SOI MOS is divided into partially depleted SOI MOS (PDSOI) and fully depleted SOI MOS (FDSOI) according to whether the active body region is depleted or not. Generally speaking, the top silicon film of fully depleted SOI MOS is relatively thin, and the cost of thin film SOI silicon wafer is high. On the other hand, the threshold voltage of fully depleted SOI MOS is not easy to control. ...

AI Technical Summary

Problems solved by technology

[0006] H-type gate SOI MOS devices have source-body, drain-body parasitic capacitances, and parasitic resistances. As L increases, parasitic capacitances and parasitic resistances increase, affecting device performance.

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