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Fixed-point processing method and device

A processing method and a processing module technology, applied in the field of communication, can solve the problems of amplifying fixed-point signal integer bit width and decimal bit width, inaccurate fixed-point processing results, inaccurate analysis of signal variation range, etc., and achieve the effect of improving accuracy

Active Publication Date: 2012-08-01
SANECHIPS TECH CO LTD
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  • Summary
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present invention is to provide a fixed-point processing method and device to at least solve the problem of fixed-point processing due to inaccurate analysis of the range of signal variation in the above-mentioned related art, which amplifies the integer bit width and decimal bit width of the fixed-point signal, resulting in fixed-point processing. Dealing with inaccurate results

Method used

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  • Fixed-point processing method and device

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Experimental program
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Embodiment 1

[0050] This embodiment provides an affine algorithm. This embodiment combines the above embodiments and preferred implementation modes therein. In this embodiment, fixed-point processing is performed on the B-splines instance used for image warping.

[0051] In this embodiment, the B-splines basic function B 0 , B 1 , B 2 and B 3 They are defined as follows:

[0052] B 0 ( u ) = 1 6 ( 1 - u ) 3 , B 1 ( u ) = 1 6 ( 3 u 3 - 6 u ...

Embodiment 2

[0069] This embodiment provides an affine algorithm. This embodiment combines the above embodiments and preferred implementation modes therein. In this embodiment, fixed-point processing is performed on 4.2 2×2 matrix multiplication instances.

[0070] In this embodiment, the 2×2 matrix is ​​as follows: y 00 y 01 y 10 y 11 = a 00 a 01 a 10 ...

Embodiment 3

[0097] This embodiment provides an affine algorithm. This embodiment combines the above-mentioned embodiments and preferred implementation modes therein. In this embodiment, the polynomial function instance is subjected to fixed-point processing.

[0098] These 8 polynomial functions in the present embodiment are listed in table 6, wherein " X " of column " Input ranges " represents from x 1 to x m The input signal variation range.

[0099] Table 6 List of polynomial functions

[0100]

[0101] Specifically, the output range analysis results using AA and RAA are listed in Table 7.

[0102] Table 7 Schematic diagram of the output range of polynomial using AA

[0103]

[0104] It can be seen from the results in the table that RAA has found more accurate results of the range of variation for all these 8 polynomial functions, and the output integer bit width obtained by RAA is the same as the real integer required by the output obtained by numerical methods or nonlinear p...

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Abstract

The invention discloses a fixed-point processing method and a fixed-point processing device. The method comprises the following steps of: respectively performing signal range analysis on all floating point signals according to all paralleling condition branches divided by a control-data flow diagram of a floating point algorithm to obtain the change range of all floating point signals and a smallest integer bit width, wherein the smallest integer bit width is a smallest positive integer value which is in accordance with the condition that a fixed-point signal does not overflow; respectively performing system precision analysis on all floating point signals subjected to signal range processing operation by using the change range to obtain a smallest decimal bit width of the floating point signals, wherein the smallest decimal bit width is in accordance with the condition that a system output precision error is less than or equal to a smallest positive integer value restricted by a predetermined error; and determining a result obtained by performing the fixed-point processing on the floating-point signals by using the smallest integer bit width and the smallest decimal bit width of the same floating point signal in all floating point signals. By the method, the accuracy of the fixed-point processing is improved.

Description

technical field [0001] The present invention relates to the communication field, in particular to a fixed-point processing method and device. Background technique [0002] Algorithms of modern digital signal processing (DSP for short) systems are mostly developed using floating-point arithmetic, because the use of floating-point arithmetic can perform fast algorithm verification and prototype modeling on a general-purpose processor development platform. After the floating-point algorithm verification is completed, it can be implemented on a floating-point hardware platform such as a floating-point DSP. But if you want to get faster speed, smaller area and lower power consumption, you need the designer to convert the floating-point arithmetic to fixed-point arithmetic, so that it can be used on fixed-point hardware platforms such as Field Programmable Gate Array (Field Programmable GateArray, FPGA for short) or Application Specific Integrated Circuit (ASIC for short). The m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/318
Inventor 张林生田万廷文小芳
Owner SANECHIPS TECH CO LTD
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