Shallow trench isolation manufacturing method

Abstract

The invention discloses a shallow trench isolation manufacturing method. The technical procedures for forming the shallow trench isolation and an active region on a silicon substrate comprise that non-crystallizing ions are injected in the position at the edge of the active region so as to allow the crystalline silicon on the surface of the active region at the injection position to be subjected to non-crystallizing processing. According to the method provided by the invention, during the following growth process of a gate oxide layer, the growth speed at the border edge is faster than that in the active region, the thinning effect of the edge thickness of the gate oxide layer is reduced, gate breakdown voltage and gate breakdown service life of a device is improved, and accordingly, the reliability of the device is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a shallow trench isolation manufacturing method. Background technique [0002] The existing shallow trench isolation (STI) process method includes an etching process for forming a shallow trench on a silicon substrate, a process for filling the shallow trench with an oxide layer for shallow trench isolation, and chemical mechanical polishing to remove the The process of grinding and removing the superfluous STI oxide layer outside the shallow trench. After grinding, the STI oxide layer formed in the shallow trench serves as electrical isolation of the active region. [0003] In the existing shallow trench isolation process, such as the technology node of 0.18 μm and below, when the gate oxide layer is grown, the thickness of the gate oxide layer is often at the boundary edge of the active region and the shallow trench isolation It is thinner than...

AI Technical Summary

Problems solved by technology

This effect not only leads to the so-called ds and V gs The curve forms a double hump, which reduces the turn-on voltage of the device and increases leakage. More importantly, the maximum voltage that the gate oxide layer can withstand decreases due to the thinning of the gate oxide layer at the edge, resulting in a Reliability failure of gate breakdown voltage (GOI) and gate breakdown lifetime (TDDB) of oxide layer

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