Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

A chip stacking and packaging technology, applied in the field of multi-layer spacer IC chip stacking and packaging, can solve problems such as poor insulation performance, affecting the height of bonding wires connecting IC chips and carrier pads, affecting chip heat dissipation, etc. , to achieve the effect of facilitating heat dissipation, solving height problems, and improving insulation performance

Active Publication Date: 2012-07-11
TIANSHUI HUATIAN TECH +1
View PDF6 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, stacked packaging is to directly stack and bond IC chips through adhesive sheets, which affects the height of the bonding wire connecting the IC chip and the carrier pad, and the insulation performance between adjacent chips is not good, which also affects the heat dissipation of the chip.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package
  • Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package
  • Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0104]The thickness of the chip thickness from the thickness of the original wafer to the final thickness of 100 μm; the thickness of the rough grinding range from the thickness of the original wafer to 150 μm +the thickness of the glue film, the thick grinding speed of 2 μm / s;The thickness of the glue membrane, the fine grinding speed is 0.6 μm / s, and the wafer thinning process is used to prevent the chip prevents warp; the roughness of the wafer after thinning is 0.10mm., Crack -proof chip processing software control technology, the speed of the cutter into the knife ≤10mm / s; the separation IC chip with a stretch membrane ring; the thinning single chip makes it the final thickness of 110 μm;From the original thickness of the single chip to 160 μm +the thickness of the glue film, the thick milling speed is 3 μm / s;The machine first on the carrier 1 of the BT substrate 16, and the upper -core machine automatically absorbs the first IC chip 3 on the electrical glue to bare the firs...

Embodiment 2

[0106] The thickness of the chip thickness from the thickness of the original wafer to the final thickness of 100 μm; the thickness of the rough grinding range from the thickness of the original wafer to 150 μm +the thickness of the glue film, the thick grinding speed of 5 μm / s;+The thickness of the glue membrane, 0.3 μm / s in the fine grinding speed, and the chip to prevent the chip's warpage process during the wafer thinning process; the roughness of the wafer after thinning is 0.05mm;Fragments and cracking chip processing software control technology, scratch the knife speed ≤10mm / s; obtain a separate IC chip with a stretch membrane ring.The thinning single chip makes its final thickness of 120 μm; During the thinning process of the single chip, the rough grinding range is from the original thickness of the single chip to 170 μm +the thickness of the glue film, and the thick grinding speed is 5 μm / s;By the thickness of 120 μm +glue film, the essence speed is 12 μm / s; the insulati...

Embodiment 3

[0108] The thickness of the chip thickness is reduced from the thickness of the original wafer to the final thickness of 100 μm; the thickness of the rough grinding range from the thickness of the original wafer to 150 μm +the thickness of the glue film, the rough grinding speed is 3.5 μm / s;100 μm +glue film thickness, fine milling speed 0.45 μm / s, and the chip to prevent the chip's warpage process during the wafer thinning process;Film; use anti -fragmented, anti -cracking chip processing software control technology, the scratch in the knife is ≤10mm / s; obtains a separate IC chip with a stretch membrane ring; a thin single chip to make it final thickDuring the process, the rough grinding range ranged from the original thickness of the single chip to 150 μm +the thickness of the glue film, and the thick grinding speed was 4 μm / s;The insulating glue is first on the carrier 1 of the BT substrate 16 by the adhesive pinstonus.And use the anti -departure baking process for 175 ° C to ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Flow lengthaaaaaaaaaa
Roughnessaaaaaaaaaa
Login to view more

Abstract

The invention discloses a multilayer spacer type IC (Integrated Circuit) chip stacked package of a substrate and a production method of the package. The package comprises a BT (Bismaleimide Triazine) substrate, wherein at least two IC chips are bonded onto a carrier of the BT substrate, all the IC chips are stacked and bonded in sequence, a bonding pad on each IC chip is connected with a bonding pad on the BT substrate through a bonding wire, a plastic package body is fixedly packaged on the BT substrate, and a spacer is bonded between every two adjacent IC chips. The production method comprises the steps of: thinning and scribing wafers and the spacers, bonding the IC chips onto the carrier of the BT substrate, then bonding the spacers onto the IC chips, and bonding the IC chips onto the spacers again to make the stacking layer number meet a use requirement, wherein the processes of baking, plasma cleaning and pressure welding are needed once each IC chip is bonded; and then bonding the IC chips continuously, and performing subsequent procedures by adopting the prior art to prepare the multilayer spacer type IC chip stacked package of the substrate with the required layer number. According to the package disclosed by the invention, the height of the bonding wire is not influenced, and the heat radiation and insulation performances of the chips are improved.

Description

Technical field [0001] The present invention belongs to the field of electronic information automation component manufacturing technology. It involves an IC chip integrated circuit packaging part, which specifically involves a multi -layer IC chip stacking part of a substrate.production method. Background technique [0002] With the expansion of the demand for various mobile phone markets that are smaller, lighter and more efficient and the growth of electronic devices of Palm Computer (PAD), it has promoted the smaller and more functional development of electronic packaging technology.The product is smaller, lighter, and more functional, and it is more and more valued by customers of various packaging companies. Various mobile phone digital cameras, various smart cards and portable instruments are the application fields of stacking packaging products.The multi -functional technology of mobile phones has promoted the rapid development and technological improvement of stack packag...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L25/00H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L2924/15311H01L2924/181H01L2224/32145H01L2224/45144H01L2224/45147H01L2224/48227H01L2224/73265H01L2924/00014H01L2924/00012H01L2924/00
Inventor 郭小伟朱文辉慕蔚王永忠
Owner TIANSHUI HUATIAN TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap