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MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof

A technology for MOS transistors and manufacturing methods, applied in the field of MOS transistors and their manufacturing, capable of solving problems affecting transistor channel mobility, junction capacitance, and junction leakage current, etc., achieving elimination of oxidation-enhanced diffusion effects and suppression of transient enhanced diffusion effects Effect

Inactive Publication Date: 2012-03-14
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In practice, it has been found that the MOS transistors fabricated by existing methods have the defect of Transient Enhanced Diffusion (TED), which not only causes the Short Channel Effect (SCE) of the transistor ) and reverse short channel effect (Reverse Short Channel Effect, RSCE), and affect the transistor channel mobility, junction capacitance and junction leakage current

Method used

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  • MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof
  • MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof

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Embodiment Construction

[0039] The inventors found that in the prior art method for forming a MOS transistor, before forming the source / drain extension region and the pocket-shaped implant region, an oxidation process is performed to form an oxide layer on the periphery of the gate structure to protect the gate, but the The oxidation process can form defects in the semiconductor substrate, which is known as the Oxidation-Enhanced Diffusion (OED) effect. Defects caused by the oxidation-enhanced diffusion effect will diffuse in the subsequent annealing process, causing the dopant ions in the source / drain extension region and the pocket implant region to diffuse, causing a transient enhancement effect and enhancing the short channel of the device effect and the reverse short channel effect.

[0040] After research, the inventors found that if an oxide layer is formed on the periphery of the gate structure, ion implantation is performed in the pocket implantation region, and non-impurity ions (such as ca...

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Abstract

The invention provides an MOS (Metal-Oxide-Semiconductor) transistor and a manufacturing method thereof. The method comprises the following steps of: providing a semiconductor substrate, wherein a gate structure is formed on the semiconductor substrate; carrying out carbon ion implantation on the semiconductor substrates at two sides of the gate structure to form a defect adsorption zone; carrying out an oxidation process to form an oxide layer covering the gate structure; and sequentially forming a source / drain extension zone and a baggy implantation zone surrounding the source / drain extension zone in the semiconductor substrates at the two sides of the gate structure, wherein the size of the baggy implantation zone along the channel length direction is less than or equal to the size of the defect adsorption zone. In the invention, carbon ions are formed before the oxidation process is carried out; and by utilizing the defects formed by carbon ion adsorption and oxidation processes, the oxidation enhanced diffusion effect and the transient enhanced diffusion effect are eliminated, and the short channel effect and the adverse short channel effect are improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a MOS transistor and a manufacturing method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Please refer to Figure 1 to Figure 3 , is a schematic cross-sectional structure diagram of a manufacturing method of a MOS transistor in the prior art. [0004] Please refer to figure 1 , providing a semiconductor substrate 100, forming isolation structures 101 in the semiconductor substrate 100, the semiconductor substrate 100 between the isolation structures 101 is an active region, and forming a doped well in the active region (not shown), the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78H01L29/06
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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