Techniques for non-overlapping clock generation

Abstract

Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non- overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non- overlapping time (tnlp) that is independent of manufacturing process variations.

Description

technical field [0001] The present invention relates generally to the field of clock generation circuits, and in particular, to non-overlapping clock generation circuits. Background technique [0002] Typically, clock generation circuits are used to clock synchronous digital circuits such as analog-to-digital converters (ADCs). A clock generation circuit provides a repetitive signal with a constant period. During a single clock signal period, the clock signal has a first phase and a second phase. Typically, a clock generation circuit provides an inverted clock signal and a non-inverted clock signal. The clock generation circuit also typically provides a delayed clock signal. [0003] One type of clock signal is a non-overlapping clock signal. Non-overlapping clock signals are often used in switched capacitor integrator circuits. The non-overlapping clock generation circuit provides a non-inverted clock signal and an inverted clock signal that transitions before the dela...

AI Technical Summary

Problems solved by technology

The extra non-overlap time and phase delay time in slow corner conditions consumes the active time of the clock and requires faster stabilization of the switched capacitor integrator

Therefore, more current is consumed for the op-transconductance amplifier in the switched capacitor integrator

Also, as the switched capacitor integrator sampling frequency (fs) increases, the non-overlap time and phase delay become more significant relative to the active time of the clock signal

Images