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Vector data access control method and vector memory that support limited sharing

A control method and vector technology, applied in the direction of electrical digital data processing, instruments, machine execution devices, etc., can solve the problems of reducing calculation efficiency and increasing code volume, and achieve the goal of improving memory access efficiency, reducing power consumption, and low hardware cost Effect

Active Publication Date: 2011-12-14
NAT UNIV OF DEFENSE TECH
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  • Application Information

AI Technical Summary

Problems solved by technology

If the vector memory only supports data-aligned access operations, 2*64=128 shuffling operations need to be added, which not only reduces the computational efficiency, but also greatly increases the amount of code

Method used

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  • Vector data access control method and vector memory that support limited sharing
  • Vector data access control method and vector memory that support limited sharing
  • Vector data access control method and vector memory that support limited sharing

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Embodiment Construction

[0042] Such as figure 1 As shown, the implementation steps of the vector data memory access control method supporting limited sharing in the embodiment of the present invention are as follows:

[0043] 1) Unified addressing of the N-way vector memory banks of the vector memory;

[0044] 2) Obtain the memory access information of the vector memory access instruction, decompose the vector address in the memory access information into a row address and a shared shift address, copy and expand the row address corresponding to the N-way vector memory bank addressing into N row addresses, and N row addresses are shifted and cyclically sorted according to the shared shift address, and combined with the memory access information to generate N sets of memory access information;

[0045] 3) Send the shared shift address and N sets of memory access information to the memory access pipelines of each vector memory bank; if the current vector memory access instruction is a read instruction...

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Abstract

The invention discloses a vector data access and storage control method supporting limited sharing and a vector memory. The method comprises the following steps of: 1) uniformly addressing the vector memory; 2) acquiring the access and storage information; performing the decomposition, expansion and displacement circular arrangement on the vector address in the access and storage information so as to generate N sets of access and storage information; and 3) respectively sending the N sets of access and storage information to the access and storage flow line of the vector memory; and if the current vector access and storage command is the reading command, performing the opposite displacement circular arrangement on the N paths of writing-back data according to the shared displacement address to obtain the N sets of writing-back data and send the data to the corresponding vector processing unit in the vector processor. The vector memory comprises a vector address generator, a vector memory unit and an access and storage management control unit; and the access and storage management control unit comprises a vector address arrangement unit and a vector data arrangement unit. The method has the advantages of realizing the hardware at low cost, and supporting the limited sharing of the vector data and the non-aligned access.

Description

technical field [0001] The invention relates to the technical field of vector processors of computer architecture, in particular to a vector data access control method and a vector memory that support limited sharing in a vector processor for wireless communication applications. Background technique [0002] With the development of 4G wireless communication technology and integrated circuit technology for data and computing-intensive applications, vector processors based on Software Defined Radio (SDR) usually use Very Long Instruction Word (VLIW) Architecture, the vector processing unit (Vector Processing Unit, VPU) composed of multiple vector processing units is integrated on the chip, and the calculation operation is performed in SIMD mode to develop the instruction-level and data-level parallelism of the vector processor and meet the real-time data processing requirements for the application target. Therefore, how to provide sufficient data bandwidth for the vector proc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F9/38
Inventor 陈海燕陈书明陈跃跃刘胜黄远广刘仲万江华陈胜刚孙书为张凯王丽萍
Owner NAT UNIV OF DEFENSE TECH
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