Controlled silicon for large-size silicon chip employing plastic entity package and packaging process thereof

Abstract

The invention relates to a controlled silicon for a large-size silicon chip employing a plastic entity package and a packaging process for the controlled silicon. The controlled silicon comprises a copper substrate and pins; a silicon chip is welded on the copper substrate through a lead-tin solder; an aluminum wire internal lead is welded on the silicon chip; the aluminum wire internal lead is plastically packaged through a plastic material; and a plastic groove is formed between the pins. The invention also relates to a process for packaging the controlled silicon for the large-size siliconchip employing the plastic entity package. The method comprises the following steps of: sintering, cleaning, welding, packaging, cutting ribs and testing. The invention has the advantages that: the process is simple and has the advantages of low thermal resistance and low state voltage drop, and the product reliability is improved.

Description

technical field [0001] The invention relates to a thyristor in which a large-size silicon chip is encapsulated by a plastic entity. [0002] The invention also relates to a packaging technology of a thyristor in which a large-size silicon chip is packaged with a plastic entity, and belongs to the technical field of packaging of semiconductor devices. Background technique [0003] At present, the chip size of the silicon controlled rectifier in the plastic physical package generally does not exceed 7×7mm. The main factor limiting the chip size of the plastic physical package is that the expansion coefficients of the three materials, the chip, the copper base plate, and the plastic encapsulant, are greatly different. Silicon chips packaged into products will have large plastic curing stress and thermal stress, which is extremely detrimental to the reliability of the product, so the packaging pass rate and reliability of this type of product are relatively low. However, becaus...

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Problems solved by technology

[0003] At present, the chip size of the silicon controlled rectifier in the plastic physical package generally does not exceed 7×7mm. The main factor limiting the chip size of the plastic physical package is that the expansion coefficients of the three materials, the chip, the copper base plate, and the plastic encapsulant, are greatly different. Silicon chips packaged into products will have large plastic curing stress and thermal stress, which is extremely detrimental to the reliability of the product, so the packaging pass rate and reliability of this type of product are relatively low

However, because products with plastic physical packaging are more convenient to install and connect electrodes in use, some people in the industry have been pursuing physical packaging of larger chips. The addition of molybdenum sheet, which has a similar expansion coefficient to single crystal silicon, is beneficial to reduce the stress caused by the difference in expansion coefficient between the silicon chip and the copper base plate, and the plastic packaging compound. However, due to the addition of two layers, the thermal conductivity is relatively small and the resistivity is relatively large. The metal sheet and two layers of solder will significantly increase the on-state voltage drop and thermal resistance of the device, which will limit the power of the device to a certain extent.

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