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TCAD simulation calibration method of SOI field effect transistor

A technology of field effect transistors and calibration methods, applied in special data processing applications, semiconductor/solid-state device testing/measurement, instruments, etc., can solve the problem of affecting the reliability and accuracy of TCAD simulation, and the TCAD simulation results cannot be provided by process and device development Effective guidance and other issues

Inactive Publication Date: 2011-09-14
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Application Information

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Problems solved by technology

These have greatly affected the credibility and accuracy of TCAD simulation, making the TCAD simulation results unable to provide effective guidance for the development of actual processes and devices

Method used

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  • TCAD simulation calibration method of SOI field effect transistor
  • TCAD simulation calibration method of SOI field effect transistor
  • TCAD simulation calibration method of SOI field effect transistor

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Embodiment Construction

[0028] Further illustrate the TCAD calibration method of the present invention below in conjunction with accompanying drawing:

[0029] The inventor of the present invention conducts error analysis on the preliminary TCAD simulation results of SOI field effect transistors, and finds that: compared with the WAT test data, for the key electrical parameters threshold voltage Vt and saturation current Idsat of MOS devices with different channel lengths, TCAD simulation The large errors in the results are mainly due to the distribution of implanted impurities in the well region, the distribution of implanted impurities in the source / drain lightly doped extension region, the distribution of implanted impurities in the source / drain region, the morphology of the sidewall isolation structure and the gate structure in the device simulation. The deviation of the oxide layer thickness Tox value is caused. Among them, the distribution of implanted impurities in the well region and the Tox ...

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Abstract

The invention discloses a TCAD (technology computer aided design) simulation calibration method of an SOI (signal operation instruction) field effect transistor. The process simulation MOS (metal oxide semiconductor) device structure of different channel length Lgate is obtained through building a TCAD process simulation procedure, on the basis, the process simulation MOS device structure is calibrated according to the transmission electron microscope TEM (tranverse electric and magnetic field) test result of the practical device, the secondary ion mass spectroscopy SIMS (secondary ion mass spectroscopy) test result, the CV test result, the WAT test result and the square resistance test result, thus finishing the TCAD simulation calibration on the key electrical parameters of the SOI field effect transistor. The calibration method can enable the TCAD simulation results of the key parameters Vt and Idsat of the MOSFET (metal-oxide-semiconductor field effect transistor) of all kinds of sizes in the same SOI process to achieve a high-precision requirement with the error smaller than 10 percent, and can realize accurate and effective forecast under a plurality of Split conditions, thus providing a powerful guidance for the development and optimization of the new process flow.

Description

technical field [0001] The invention relates to semiconductor device simulation technology, in particular to a TCAD simulation calibration method for SOI field effect transistors, belonging to the field of microelectronic devices. Background technique [0002] The computer-aided design of integrated circuit technology and device technology (abbreviated as TCAD) is an important part of integrated circuit device design and virtual manufacturing, and a powerful tool for rapid analysis of IC technology and device characteristics. IC TCAD mainly includes process simulation and device simulation. The process simulation mainly uses the process flow and process parameter simulation to obtain the virtual device structure, impurity distribution, junction depth, sheet resistance, etc., and the device simulation mainly uses the device physical model and test conditions in virtual The device characteristic parameters and curves are obtained by simulating the device structure. The applic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66G06F17/50
CPCG06F17/5036H01L22/20G06F17/5081G06F30/367G06F30/398
Inventor 柴展陈静罗杰馨伍青青王曦
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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