Quasi-cyclic low density parity-check code (QC-LDPC) decoder and decoding method

Abstract

The invention discloses a quasi-cyclic low density parity-check code (QC-LDPC) decoder. The QC-LDPC decoder is applied to solid state disk error correction systems, and comprises a syndrome calculation module, a judgment control module, a searching module and an overturn control module, wherein the syndrome calculation module is used for calculating the syndrome of a code sequence to be decoded; the judgment control module is used for judging whether the syndrome is an all-zero vector or not, and controlling to finish the syndrome calculation and outputting the current code sequence as a decoding result if the syndrome is the all-zero vector; the searching module is used for calculating the set of the number of code elements which do not meet a check equation in the code sequence to be decoded and searches the position of a maximal value in the set when the syndrome is not the all-zero vector; and the overturn control module is used for overturning the code element which corresponds to the position of the maximal value in the set in the code sequence to be decoded, and inputting an updated code sequence to be decoded into the syndrome calculation module. The invention correspondingly provides a QC-LDPC decoding method. Thus, by using the decoder and the decoding method, the syndrome calculation can be controlled to be finished when error correction is finished, and the decoding period and decoding delay are lowered.

Description

technical field [0001] The invention relates to a solid-state hard disk error correction system and method, in particular to a quasi-cyclic low-density parity-check code (QC-LDPC) decoder and a decoding method. Background technique [0002] At present, the error correction technology applied to solid-state hard drives is mainly BCH technology. The encoding process is realized through linear feedback shift registers. The number of registers is proportional to the error correction capability requirements; is the key equation solving and finally the money search process. The decoding process of this technology is complicated, which leads to complex hardware implementation circuits, and the price of delay and chip area needs to be paid. As the technological level improves, the page unit of the flash memory array increases, the sector size for error correction develops from 512B to 1KB, and the code length increases and the error correction capability also increases. With the i...

AI Technical Summary

Problems solved by technology

The traditional BCH error correction technology has a fixed number of error correction bits for a specific application, which means that even if the number of errors in the decoding process is less than the set number of error correction bits, the clock consumed by the adjoint calculation in the decoding process Cycles are not reduced, unnecessary clock cycles are wasted

More bit information is stored on a floating gate transistor unit, and the storage density is greatly improved, requiring a lower bit error rate. These requirements pose a huge challenge to BCH, and the implementation becomes complicated or even difficult, while the error correction performance is reduced. severe decline

[0004] In summary, the existing solid-state hard disk error correction system and method obviously have inconvenience and defects in actual use, so it is necessary to improve it.

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