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Bidirectional high speed FIFO storage implemented on the basis of FPGA

A memory and high-speed technology, which is applied in the direction of instruments, data conversion, electrical digital data processing, etc., can solve the problems of low integration and slow speed, and achieve the effects of reducing power consumption, fast speed, and system size

Inactive Publication Date: 2010-09-15
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Abstract
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  • Application Information

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Problems solved by technology

[0005] In view of this, the main purpose of the present invention is to provide a kind of bidirectional high-speed FIFO memory based on FPGA, to adopt FPGA to realize bidirectional high-speed FIFO memory, solve current bidirectional FIFO interface and all adopt discrete components to realize, integration degree is not high and speed is slow question

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  • Bidirectional high speed FIFO storage implemented on the basis of FPGA
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  • Bidirectional high speed FIFO storage implemented on the basis of FPGA

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Embodiment Construction

[0039] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040]The bidirectional high-speed FIFO memory based on FPGA provided by the present invention adopts two unidirectional FIFO units to meet the requirement that the first bus A and the second bus B may read and write at the same time, and a communication mailbox is added to solve the problems of special data. Contradictions that are directly output after queuing. One end of the FIFO (i.e. the first one-way asynchronous FIFO read-write module 1 and the second one-way asynchronous FIFO read-write module 2) and the communication mailbox is connected with the first asynchronous bus interface module 3, and the other end is connected with the second asynchronous bus interface Module 4 is connected. The first asynchronous bus i...

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Abstract

The invention belongs to the storage technical field and discloses a bidirectional high speed FIFO storage implemented on the basis of FPGA. The bidirectional high speed FIFO storage comprises a first asynchronous bus interface module, a first communication box, a first unidirectional asynchronous FIFO read-write module, a second asynchronous bus interface module, a second communication box and a second unidirectional asynchronous FIFO read-write module. The function of the bidirectional high speed FIFO storage is similar to that of SN74ABT3614 produced by Texas instruments, and programmable output line width, synchronous or asynchronous input output clock and bidirectional mail box communication function can be realized. The invention has the advantages that: FPGA is utilized to realize bidirectional FIFO module, steady speed is fast, implementation is easy and occupying resource is less, occupancy rate of programmable logical module in Xilinx Spartan3 series FPGA is less than 7%, and integration with other logical functions is easy, thus being capable of effectively improving system integration, reducing system size and reducing power consumption.

Description

technical field [0001] The invention relates to the technical field of FIFO memory, in particular to a bidirectional high-speed first-in-first-out (FIFO) memory realized based on a field programmable gate array (FPGA). Background technique [0002] FIFO plays a pivotal role in modern digital systems. It provides a reliable guarantee for a large amount of data transmission between different clock domains. From the clock synchronization, it is divided into synchronous FIFO and asynchronous FIFO; from the directionality of transmitted data, it is divided into one-way FIFO and two-way FIFO. [0003] Currently, bidirectional FIFOs are implemented using custom chips. Not only is the speed slow, the price is relatively high, but also the system integration level is not high, and the system size and power consumption cannot be effectively reduced. FPGA is a digital integrated circuit composed of configurable logic blocks, which can be reconfigured by design engineers to achieve di...

Claims

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Application Information

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IPC IPC(8): G06F5/10
Inventor 刘蕾鲁华祥边昳
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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