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Dissociation rate matching method and device

A technology for de-rate matching and de-interleaving, applied in the field of de-rate matching methods and devices, can solve the problems of bit-level processing efficiency, inability to be effectively improved, large input data volume, etc., and save time for reading data , Save the time of judging the address and improve the processing efficiency

Active Publication Date: 2010-07-28
LEADCORE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In the above-mentioned prior art, due to the use of the processing method of accumulating the repeated bits one by one, the bit-level processing efficiency is limited by the huge amount of input data and cannot be effectively improved

Method used

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  • Dissociation rate matching method and device

Examples

Experimental program
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Embodiment 1

[0053] Embodiment 1. On the basis of the above-mentioned division of multiple sub-RAMs, refer to figure 1 , the method provided by the embodiment of the present invention includes the following steps:

[0054] S101: According to the address of the received input data, determine the sub-RAM where the input data should be stored and the position in the sub-RAM, and store each repeated input data in parallel in different sub-RAMs;

[0055] Through this step, it is possible to store repeated data in different sub-RAMs, and since each bit of data should be stored in which sub-RAM and where it should be stored in the sub-RAM can be determined, therefore, it can be parallelized Store data into each sub-RAM. Wherein, the sub-RAM where the input data should be stored and the location in the sub-RAM can be determined according to the length of the data and the number of times of repeated sending.

[0056] see figure 2 , which is a schematic diagram of the implementation structure of...

Embodiment 2

[0073] In practical applications, if the receiving end finds that the received input data has errors, it may perform HARQ (Hybrid-ARQ, hybrid automatic retransmission operation), that is, it needs to request the sending end to resend the data. Note that the concept of resending data here is different from the concept of repeatedly sending data described above. The repeated transmission mentioned above refers to increasing the length of data for subsequent symbol-level processing during one transmission; and retransmission means that if an error is found during one transmission, the sending end performs the same operation as the first The operation of the same configuration in the first transmission, that is, when the data is resent after receiving the HARQ request each time, a string of data needs to be repeatedly sent multiple times.

[0074] In order to improve the accuracy of the received data, the data received again after the HARQ request can often be combined with the da...

Embodiment 3

[0082] Since the process of de-rate matching is from the k in the soft buffer (IR_BUFFER) of the current code block 0 After reaching the last value of the soft buffer, it increases from position 0 until k in the soft buffer 0 -1 position end, iterate over all positions in the soft buffer. For the data outside the soft buffer after interleaving, it is discarded during the rate matching encoding, and these discarded data need to be filled with zeros to replace the rate matching solution, which requires the process of solving the rate matching to process three bit streams All data of (systematic bit, parity bit 1, parity bit 2) (total (3*32* interleaving matrix row number=K w ) data) to traverse. In downstream processing, the soft buffer size per code block That is N cb always less than or equal to K w , and in some cases the difference between these two values ​​is very large, for example: in LTEFDD system, when the number of code blocks is 20, N IR / C is 7733, while K w...

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Abstract

The invention discloses a dissociation rate matching method and a device, which are used for a dissociation rate matching system. The system comprises a plurality of sub-random access memories (sub-RAMs) for storing input data, wherein the number of the sub-RAMs is the same as the maximum number of repeated sending supported by a receiver of a matching system. The method comprises the following steps: determining the sub-RAM in which the input data needs to be stored and the position of the input data in the sub-RAM based on the address of the received input data, and storing the repetitive input data for each time in different sub-RAMs in parallel; determining the corresponding address of the data serial number in a soft buffer at the sending end of the matching system in the input RAM of a decoder by the deinterleaving calculation; determining and withdrawing the input data from the sub-RAM when the corresponding address in the input RAM needs to be filled with data; and determining the data to be written based on the withdrawn input data, and writing the data to be written in the corresponding address in the input RAM. By using the invention, the processing efficiency at the bit level can be improved.

Description

technical field [0001] The present invention relates to the field of communication technologies, in particular to a rate matching method and device. Background technique [0002] Rate matching means that bits on the transmission channel are repeated or punctured to match the carrying capacity of the physical channel. Punching is to delete the current bit as invalid data, and at the same time, move the following bits forward one by one; repetition is to achieve the effect of repetition by cyclically fetching numbers in the soft buffer, so the repeated data is not adjacent . The de-rate matching algorithm, on the contrary, restores the bits that were knocked out and merges the repeated bits so that it can be decoded correctly. [0003] Among them, in the process of de-rate matching, it is necessary to process each coding block output by cascading decoding blocks separately. The following three processes mainly need to be completed: First, it is the process of de-matching the...

Claims

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Application Information

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IPC IPC(8): H04L1/00H04L1/18
Inventor 李依扬
Owner LEADCORE TECH
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