Electrostatic protection structure and manufacturing method thereof

Abstract

The invention discloses an electrostatic protection structure, which comprises a P-type substrate and an N-type deep well on the P-type substrate, wherein an N well is further arranged below a second N+ diffusion region and a fourth field oxide region and in the range of the N-type deep well; and an N-type secondary diffusion region is further arranged below the N well. The invention further discloses a manufacturing method for the electrostatic protection structure, wherein the N-type secondary diffusion region is formed by an ion implantation process after the formation of the field oxide region and before the formation of the N well. The electrostatic protection structure and the manufacturing method can ensure uniform distribution of current during current discharge by arranging the N-type secondary diffusion region under the N-type well, so physical damage caused to the electrostatic protection structure is avoided and the stability of the device is improved.

Description

technical field [0001] The invention relates to an antistatic protection structure of a semiconductor device, and also relates to a manufacturing method of the antistatic protection structure of a semiconductor device. Background technique [0002] The damage of static electricity to electronic products has always been a problem that is not easy to solve. The most commonly used ESD protection structure today uses the GGNMOS structure (Ground Gate NMOS, gate grounded NMOS), but it is mainly used in the electrostatic protection of low-voltage circuits. At present, the more popular electrostatic protection structure applied to high-voltage circuits is lateral diffusion NMOS (Lateral Diffusion NMOS), such as figure 1 As shown, it includes a P-type substrate 1 and an N-type deep well 2 on it, and a P well is arranged on the N-type deep well 2, and the P well includes a high-voltage P well 3 and a high-voltage P well 3 contained in the high-voltage P well 3. A low-voltage P well ...

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Problems solved by technology

However, it is found in the research that a large electric field is easily generated at the intersection of the N+ diffusion region of the drain and the field oxide region near the gate side, such as figure 1 As shown by the middle arrow, the concentration of N-type impurities in the drain region is higher on the surface than in the deep layer of silicon, so that the path resistance of the horizontal triode is smaller than that of the vertical triode, and more ESD current passes through the conduction path of the horizontal triode. , a large current will also pass through this junction, generating a lot of heat. When the temperature is too high, it will cause physical damage to the field oxidation zone here

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