Semiconductor device and manufacture method thereof

Abstract

The invention relates to a semiconductor device and a manufacture method thereof, wherein the manufacture method comprises the following steps of: providing a semiconductor underlay; etching the semiconductor underlay so as to form a barrier region block; forming barrier walls at both sides of the barrier region block; forming an underlay coating on the semiconductor underlay, wherein the barrierwalls and the surface of the underlay coating have fall; forming a gate oxide and a grid electrode on the underlay coating and the semiconductor underlay; carrying out low-doping ion implantation in the semiconductor underlay; carrying out rapid thermal annealing to form a low-doping source / drain region in the semiconductor underlay; forming isolation layers at opposite sides of the gate oxide and the grid electrode; and forming a heavy-doping source / drain region in the semiconductor underlay. The invention has technical scheme that the barrier walls are formed in the semiconductor underlay, thereby effectively separating the interpenetration between the source region and the drain region, obviously improving the short channel effect of the semiconductor device, avoiding the generation ofa punch-through effect between the source region and the drain region and improving the electrical behaviour of the semiconductor device. Meanwhile, a bigger process regulating space is provided for the reduction of junction capacitance and the enlargement of process window in the ultra shallow junction process.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device and the semiconductor device. Background technique [0002] With the rapid development of Ultra Large Scale Integration (ULSI), the manufacturing process of integrated circuits has become more and more complicated and refined. In order to improve integration and reduce manufacturing costs, the critical dimensions of semiconductor devices continue to decrease, and the number of semiconductor devices per unit area of ​​a chip continues to increase. While the critical dimensions of semiconductor devices are reduced, the patterns of semiconductor devices are also continuously miniaturized. [0003] For MOS transistors, when the channel length L of the MOS transistor is shortened to the sum of the source and drain depletion layer widths (W s +W d ) is compared, the device will deviate from the behavior of the long ...

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the present invention is: how to improve the junction capacitance and junction leakage in the short channel effect in the manufacturing process of semiconductor devices, and avoid the problems of punch-through effect and electrical performance deterioration between source / drain regions

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