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SOC (system on chip) chip and method for testing same

A system-on-chip, chip technology, applied in the field of communications, can solve the problem of inability to quickly test SOC chips effectively, and achieve the effect of improving accuracy and efficiency

Active Publication Date: 2010-05-26
SANECHIPS TECH CO LTD
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Problems solved by technology

[0005] Considering the problem that the function of the SOC chip cannot be effectively and quickly tested at present, the present invention is made, for this reason, the main purpose of the present invention is to provide a system-on-chip chip and a method for testing the system-on-chip chip, to solve the problems in the related art the above question

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  • SOC (system on chip) chip and method for testing same
  • SOC (system on chip) chip and method for testing same
  • SOC (system on chip) chip and method for testing same

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Embodiment Construction

[0026] Functional Overview

[0027] In the related art, since the system-on-chip cannot be tested quickly and effectively, the present invention improves the structure of the system-on-chip, and proposes a detection method based on the improved system-on-chip, and the specific processing is: external The test signal generator provides test vectors to the baseband chip; the first IO MUX and safety insurance wind the signal of the external test signal generator to the AHB bus MUX; the AHB bus MUX selects and drives different modules; The result of setting or accelerator is sent to the result and status module, and connected to the external test data analyzer by the second IOMUX; the external test data analyzer compares the received information with the known result obtained by simulation to judge whether the test is passed.

[0028] Before the above-mentioned processing procedure of the present invention is described in detail, the chip structure in the prior art is firstly desc...

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Abstract

The invention discloses SOC (system on a chip) chip and method for testing the same. The SOC chip comprises first IO MUXs, at least one result and state module and at least one second IO MUX, wherein the first IO MUXs are used for transmitting test data from an external test signal generator to a bus MUX, and the bus MUX selects and drives peripheral equipment or an accelerator to test; the result and state modules are used for receiving results of tests carried on the peripheral equipment and / or the accelerator and sending the test results to the corresponding second IO MUXs; and the second IO MUXs are used for sending the test results to an external test data analyzer so as to analyze the test results. The technical scheme solves the problem that the SOC chip cannot quickly test and improves the correct rate and the efficiency of the chip test so as to quickly select chips with sound functions.

Description

technical field [0001] The present invention relates to the communication field, and in particular, relates to a system-on-chip chip and a method for testing the system-on-chip chip. Background technique [0002] At present, integrated circuit system-on-chip (System On Chip, referred to as SOC) is widely used in communication, aviation, control and other fields, and the integration level of SOC is getting higher and higher. A multi-core SOC including a Micro Controller Unit (MCU for short) and a Digital Signal Processing (DSP for short). [0003] In the related art, for complex signal processing, it is realized by hanging on the bus of DSP or MCU through the method of hardware accelerator. When such complex SOC chips leave the factory, methods such as boundary scan and tester are usually used to detect whether the chips are good or bad. [0004] This general testing method cannot fully ensure the function of the chip after testing, especially the function of the above-ment...

Claims

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Application Information

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IPC IPC(8): G01R31/317
Inventor 陶建平
Owner SANECHIPS TECH CO LTD
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