Data buffer of high-speed data exchange interface and data buffer control method thereof

Abstract

The invention discloses a data buffer of a high-speed data exchange interface and a data buffer control method thereof. The data buffer comprises a data storage unit, a buffer read-write control unit, a state register and a bit width conversion unit, wherein the data storage unit is used for buffering data among asynchronous clock zones; the buffer read-write control unit is used for controlling the read and write operations of the data buffer unit; the state register is used for controlling the exchange with the buffer read-write control unit and the state information; and the bit width conversion unit is used for carrying out bit width conversion when the bit width of the data storage unit and the bit width of a bus are different. The data buffer control process is achieved as follows: transmitting a read-write instruction to the buffer read-write control unit by a pack processing engine in a mode of facing to a unit; saving the storage state of the buffer by a transmitting mark state register; controlling the data transmission by buffer data; and realizing ordered data transmission by a self-increasing pointer. The invention has the advantages of strong control flexibility and high data transmission efficiency, and is used for multiport high-speed data exchange of a network processor and data link layer equipment.

Description

technical field [0001] The invention belongs to the technical field of data communication and relates to a data buffer, in particular to a data buffer for a high-speed exchange interface and a data buffer control method thereof, which are used for data exchange between a network processor and a link layer device. Background technique [0002] With the development of network communication technology, the data traffic of the Internet is increasing exponentially, and the network bandwidth has increased from 2Gbps a few years ago to 40Gbps now, which requires higher and higher data processing capabilities of switches and routers. In addition, , in order to adapt to different working environments and network service quality QoS requirements, network switching equipment is also required to have more flexible programmability and scalability. Therefore, network processors have gradually replaced traditional General-purpose processors and application-specific integrated circuits are ...

AI Technical Summary

Problems solved by technology

[0005] 1. The data access of the FIFO buffer is strictly in the order of first-in-first-out, and the data must be read out in the order in which they are written. However, network processors usually use multiple parallel processing cores or threads to process data packet forwarding of multiple ports. This strict sequence requirement limits the flexibility of parallel processing systems for multi-port processing;

[0006] 2. The storage state of FIFO is translucent, and the outside world can only obtain the basic storage state of FIFO through signals such as empty full flag or half full half empty, and the generation of these flags requires very complex logic circuits, such as gray code conversion, address comparison operations, etc.

[0007] 3. The network processor usually processes network data packets in the form of block transmission. For example, it needs to receive 64 bytes of network data to perform a reception. This block transmission can adapt to the characteristics of IP data packets, and the access unit of FIFO Same as the data width of RAM, a data storage unit can only be a small length of 32 bits or 64 bits, which is not conducive to supporting block transmission

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