Realization method for improving chip yield

Abstract

The invention provides a design method for improving chip yield. In the method, chip yield is improved by adopting the methods of dynamic memory array redundant structure configuration, array defect reparation and power-on protection circuit. The design of the dynamic memory array redundant structure configuration comprises an on-ship memory array logical structure design, an on-ship memory array territory structure design, a top layer fuse control logic module and a protection circuit design; a defective column unit is replaced by designing a redundant column array, and a defective row unit is replaced by designing a redundant row array in the dynamic memory array; when a certain column with faults and defects is discovered in the testing process for the storage parts, the top layer fuse control logic module and the protection circuit are connected with a standby redundant column array or redundant row array by programming a fuse unit connected with a column decoder so as to replace the corresponding part with faults and defects so that fault reparation of the whole chip and improvement of chip yield are realized.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a structural design implementation method for improving chip yield. Background technique [0002] With the rapid development of integrated circuit technology, in order to meet people's needs, large-capacity storage capacity has increasingly become a basic feature of high-performance microprocessors, which requires embedding large-capacity memories inside the chip. It is possible to build more powerful chips to better accommodate the greater demand for memory in today's various chip applications, but on the other hand, it is also caught in the dilemma of larger chip sizes and lower yields. Because the increase of the internal memory ratio of the chip is the main reason for the failure of the chip, the process deviation caused by the higher and higher integration density is one of the main reasons for the decrease of the chip yield. The increase in the number of memories o...

AI Technical Summary

Problems solved by technology

Multiple chip castings not only increase the cycle of design, verification, and testing, but also the expensive chip production costs also cause cost losses in the entire chip R&D and production process

Images