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FPGA-based solid-state power controller inverse time over-current protection device

A protection device and solid-state power technology, which is applied in the direction of protection against overcurrent, can solve the problems of poor anti-electromagnetic interference performance, insufficient stability, and insufficient precision, and achieve strong real-time performance, strong stability, and modular The effect of simple structure

Inactive Publication Date: 2009-12-09
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the inverse time control of this method is determined by the resistance and capacitance values, there are disadvantages: low precision, poor reliability, large power consumption, etc., which limits its application;
For example, the patent No. 200420071350 proposed by Guangdong Kelon Electric Co., Ltd. is a single-chip system power-off protection circuit, which is realized based on this method. The disadvantages of this method are: the stability is not high enough, the precision is not high enough, and the flexibility is poor , the anti-electromagnetic interference performance is relatively poor

Method used

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  • FPGA-based solid-state power controller inverse time over-current protection device

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Embodiment Construction

[0031] The concrete realization of the present invention is to finish inside FPGA, and this FPGA uses the xcv300 of the virtex series of xilinx company, and the register described below is spliced ​​by LUT, and adder and multiplier adopt the ip core that xilinx company provides, And their operating frequency is 40MHZ, and each operation requires two clock cycles. The adder is a signed adder, and the multiplier is integer multiplication. The comparators, latches, and finite state machines used The counter and the counter are spliced ​​based on FPGA LUT, flip_flop, and slice. The memory is the block_ram block embedded in the FPGA. The size of each block_ram block is 4Kbit. The working clock of the entire FPGA is 1.818181MHZ.

[0032] The basic principle of the inverse time overcurrent protection algorithm is: the mathematical expression of the transmission line inverse time overcurrent protection characteristic curve equation is t = k ...

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PUM

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Abstract

The invention discloses an FPGA-based solid-state power controller inverse time over-current protection device, mainly solving the problems that the existing time over-current protection device is poor in reliability, high in power consumption, low in accuracy and poor in strong electromagnetic interference resistance. In the invention, a clock management module, a multiple data register group module, an FSM control module, an inverse time over-current protection module and an output control module are arranged in the interior of FPGA; wherein the multiple data register group module receives an FSM control module address signal and outputs data to the FSM control module which judges the data, the judged data enters the inverse time over-current protection module, result calculated by the inverse time over-current protection module is returned to the FSM control module which compares the returned data, the comparison result is sent to the output control module which outputs a control signal to an outside circuit, and the clock management module provides a system clock for all modules. The invention has the advantages of high accuracy, strong reliability, strong electromagnetic interference resistance, low power consumption and the like.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits and relates to solid-state power control, in particular to an inverse time overcurrent protection system, which can be used in industrial monitoring, electronic load protection, aircraft, aerospace and other fields. Background technique [0002] The solid-state power controller is a circuit load monitoring system based on semiconductors. It collects current data from the circuit load, and then judges whether the load is working normally according to the current value. When it detects that the current flowing through the load is greater than a certain fixed rated value, it will delay and shut down the load according to the current value, so as to avoid the load being damaged due to overcurrent and realize inverse time limit control. [0003] Currently, there are two inverse time protection methods for solid-state power controllers: [0004] The first prior art is the inverse time contr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02H3/08
Inventor 相征刘校伟冀晗任鹏徐连军
Owner XIDIAN UNIV
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