FPGA-based solid-state power controller inverse time over-current protection device
A protection device and solid-state power technology, which is applied in the direction of protection against overcurrent, can solve the problems of poor anti-electromagnetic interference performance, insufficient stability, and insufficient precision, and achieve strong real-time performance, strong stability, and modular The effect of simple structure
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[0031] The concrete realization of the present invention is to finish inside FPGA, and this FPGA uses the xcv300 of the virtex series of xilinx company, and the register described below is spliced by LUT, and adder and multiplier adopt the ip core that xilinx company provides, And their operating frequency is 40MHZ, and each operation requires two clock cycles. The adder is a signed adder, and the multiplier is integer multiplication. The comparators, latches, and finite state machines used The counter and the counter are spliced based on FPGA LUT, flip_flop, and slice. The memory is the block_ram block embedded in the FPGA. The size of each block_ram block is 4Kbit. The working clock of the entire FPGA is 1.818181MHZ.
[0032] The basic principle of the inverse time overcurrent protection algorithm is: the mathematical expression of the transmission line inverse time overcurrent protection characteristic curve equation is t = k ...
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