Dual mode 4/4.5 pre-divider

A prescaler and flip-flop technology, applied in the direction of electrical components, automatic power control, etc., can solve the problem of large quantization noise of the ΔΣ modulator, and achieve the effect of improving resolution, satisfying fast settling time, and reducing contribution.

Inactive Publication Date: 2009-07-08
FUDAN UNIV
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Problems solved by technology

[0010] In order to solve the problem of relatively large quantization noise of the above-mentioned ΔΣ modulator, the present invention provides a dual-mode 4/4.5 prescaler circuit, which divides the feedback voltage-controlled oscillator signal by 0.5 by sim...

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Embodiment 1

[0032] figure 2 Schematic diagram of the system structure of the fractional frequency synthesizer used in the present invention, including frequency and phase detector 100, charge pump 110, loop filter 120, voltage controlled oscillator 130, dual-mode N / N+0.5 prescaler 200 . Programmable P / S counter 150 and ΔZ modulator 160 . The output signal f can be obtained vco =[S*(N+0.5)+(P-S)*N]*f div =(P*N+0.5*S)*f div , and when the integer frequency division is locked, f div equal to f ref , so get the output signal f vco =(P*N+0.5*S)*f ref , the resolution of the output signal is increased to 0.5*f ref . In the fractional frequency division mode, since the ΔΣ modulator 160 produces a variable integer frequency division ratio, f div is not always equal to f ref , but dynamic equality. At this moment, the output of ΔΣ modulator 160 is equivalent to a quantization step on the frequency division ratio of 0.5, so its output quantization noise is relative to figure 1 Reduced ...

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Abstract

The invention relates to a dual-mode 4/4.5 dual-modulus prescaler circuit, which belongs to the phase-locked frequency synthesis technology field in IC design, and comprises four two-input AND gates, two rising edge D-triggers, two descending edge D-triggers, two flip-latches and two two-input signal selectors, wherein, two of the two-input AND gates, the rising edge D-triggers, the two descending edge D-triggers and one two-input signal selector form a prescaler logic circuit; two two-input AND gates, the two flip-latches and one two-input signal selector form a loop termination logic circuit; and the prescaler logic circuit and the loop termination logic circuit realize 4 frequency division or 4.5 frequency division under the action of external control signals. The dual-mode 4/4.5 dual-modulus prescaler circuit reduces the step length of frequency dividing ratio and the quantum step of a Delta-Sigma modulator to reach 0.5, increases the system resolution, reduces the phase noises produced by the Delta-Sigma modulator, and can increase the loop bandwidth and accelerate the system generated time with the same phase noises being kept.

Description

technical field [0001] The invention belongs to the technical field of phase-locked frequency synthesis in integrated circuit design. It relates to a frequency divider, in particular to a dual-mode 4 / 4.5 prescaler applied to a fractional frequency division phase-locked loop. Background technique [0002] The frequency synthesizer is an important module in the communication circuit, which provides a local oscillator signal for the frequency conversion of the transceiver circuit, and usually uses the phase-locked loop technology to realize the frequency synthesis. The output frequency of the traditional integer frequency synthesizer can only be an integer multiple of the input reference frequency, and the loop bandwidth is limited by the size of the input reference frequency. In system applications that require small frequency steps, it is difficult to meet the system's requirement for fast settling time. requirements. The output frequency step size of the frequency synthesi...

Claims

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Application Information

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IPC IPC(8): H03L7/18
Inventor 卢磊唐长文
Owner FUDAN UNIV
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