Outburst disorder based memory controller, system and its access scheduling method

Abstract

The invention provides a memory controller based on the burst disorder memory access dispatching, which is used to the burst disorder memory access dispatching accessed by a memory, and comprises a reading-writing queue module for storing the reading-writing memory access from a processor in a two-dimension mode, a block arbitration module for arbitrating a burst memory access from each block in each memory clock period, and an event selection module for selecting the final memory access operation from the burst of each block after arbitrated to send to the memory. The block is conducted withthe burst arbitration to dispatch the disorder memory access through changing the structure of a queue and adopting the priority expression provided by the invention, thereby increasing the data bandwidth of the memory, and reducing the executing time of the processor.

Description

technical field [0001] The invention relates to a memory controller, in particular to a memory controller based on burst out-of-order memory access scheduling. [0002] The invention also relates to a memory system based on burst out-of-order memory access scheduling. [0003] The invention also relates to a memory access scheduling method based on the burst out-of-sequence memory controller. Background technique [0004] With the continuous improvement of the performance of the processor, the data demand of the processor for the memory is increasing, and the bandwidth of the memory has become a bottleneck restricting the improvement of the performance of the processor system. The peak bandwidth of the memory is determined by the two characteristic parameters of the frequency of the memory chip and the bus width. Using a good memory access scheduling control strategy can make better use of memory bandwidth. [0005] Synchronous Dynamic Random Access Memory (SDRAM) usually...

AI Technical Summary

Problems solved by technology

Such a structure and organizational form make each access of the controller to SDRAM be based on a single write access instead of a write burst with less delay, which is a waste of memory bus bandwidth.

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