A device for extending the capacity of access queue by distribution control

Abstract

The invention discloses a device for extending the capacity of access queue by distribution control in the superscalar microprocessor, namely, in the instruction production line of the microprocessor, an access queue distributor is arranged at a register renaming station, and an access instruction transmission controller is arranged at an instruction transmission station. The access queue distributor checks whether the current new entry numbers to be distributed are matched with the access queue entry numbers loaded by access instructions in the transmission queue, when distributing the access queue entry numbers to each access instruction, if not, distributes new entry and sends the access instructions to the transmission queue; if so, does not distribute new entry and blocks the access instructions at the register renaming station. The access instruction transmission controller adds an judgement condition based on the normal instruction transmission condition when ready to transmit the access instructions, namely checks whether the access queue entry numbers loaded by the access instructions are matched with the access queue entry numbers loaded by the access instructions transmitted but not exited, if not, the transmission is allowed to transmit the access instruction to the executive parts; if so, the transmission is stopped to keep the access instructions in the transmission in the queue. The device pre-distributes the access queue occupied by these access instructions to the new access instructions prior to the exit of the access instructions, and the cache is in theexisting transmission queue, and on the premise of no coverage of access queue information, the number of the access instruction on the stream line is increased to indirectly extend the capacity of the access queue and make up the performance loss of the common access queue control methods.

Description

technical field [0001] The invention relates to a device for managing memory access queues in superscalar microprocessors emitting out of order, which can indirectly expand the capacity of the memory access queues through distributed control. Background technique [0002] In a superscalar microprocessor, memory access instruction processing usually includes several pipeline platforms such as instruction fetch, decoding, register renaming, launch, read register, address calculation, address substitution, memory access operation, and instruction exit. The latency of a store operation is indeterminate and may take multiple cycles. To improve performance, microprocessors need to support instruction out-of-order issue, out-of-order execution, and in-order retirement. To this end, the microprocessor needs to set up a special memory access queue to store the status of the memory access instructions flying between address substitution and instruction exit, and to process the order ...

AI Technical Summary

Problems solved by technology

This method can accurately control the fullness of the memory access queue, but it has two defects: First, the number of entries in the memory access queue is equal to the number of memory access instructions flying between the renaming of the register and the exit of the instruction, resulting in The number of memory access instructions flying between the time of instruction exit is less than the number of entries in the memory access queue, which cannot make full use of memory access component resources; second, memory access instructions will block non-memory access instructions from entering and launching because the memory access queue is full at the register renaming platform Queues, weaken the granularity of out-of-order emission and out-of-order execution, and reduce the utilization of execution component resources

Images