Transient voltage suppressor manufactured in silicon on oxide (soi) layer

Abstract

A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P- / P+ substrate layer disposed above the insulator layer.

Description

technical field [0001] The present invention generally relates to circuit structures and methods of making transient voltage suppressors (TVS). More specifically, the present invention relates to improved circuit structures and methods for fabricating TVSs in silicon-on-insulator (SOI) layers for providing low capacitance for TVS protection. Background technique [0002] Conventional techniques for designing and manufacturing transient voltage suppressors (TVS) still face certain technical difficulties. In particular, when standard CMOS process steps are applied to form multiple PN junction diodes on a TVS in a semiconductor substrate, inherent PNP and NPN parasitic transistors are created. During an ESD event or when a transient voltage occurs, the parasitic NPN or PNP transistor is turned on or latched as a larger voltage is applied to the TVS array. The latch-up may result in a sudden and strong voltage snap back. Sudden and large jerk returns can have the undesired ef...

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Problems solved by technology

Additionally, if Figure 2C As shown, such an implementation also creates another latch-up problem due to SCR action induced by parasitic PNP and NPN transistors

The breakdown of the main zener diode triggers the NPN to conduct, and the conduction of the NPN further conducts the SCR to cause latch-up

At high temperature, even if the NPN is not conducting, high leakage current through the NP junction of the parasitic NPN may conduct the SCR and cause latch-up

In order to suppress latch-up due to SCR action induced by parasitic PNP and NPN transistors, practical devices on semiconductor substrates require such Figure 2B The lateral extension shown may be up to a distance of 100 microns or more, and the suppression is usually not sufficiently effective

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