High speed wide range multi-mode programmable frequency divider with 50 26676056uty ratio

Abstract

A wide high speed range multimode programmable frequency divider with 50 percent of duty ratio comprises basic frequency division units cascaded with each other, a main divider stage comprising a series of or gates and used for expanding frequency driving ration range, a 2 divider stage made up of a DFF flip-flop element . A first stage basic frequency division unit in the main divider stage is a 2 / 3 / 4 frequency division unit while the rest is a 2 / 3 frequency division unit. A mode control signal output end of a second stage basic frequency division unit in the main divider stage inputs a trigger signal end of the DFF flip-flop element. A Q end of the DFF flip-flop element outputs the final output f of the frequency divider. The frequency divider has simple circuit structure, low power consumption, good effect; the output signal has low jitter characteristic; the duty ratio of a control output signal reaches 50 percent; when in even number frequency division, output duty ratio is 50 percent; when in odd number frequency division, the output duty ratio is 44.4 % at worst; along with the augment of the duty factor, the output duty ratio is closer to 50 %.

Description

technical field [0001] The invention relates to the design of a frequency divider, in particular to the technical field of designing a high-speed and wide-range multi-mode programmable frequency divider, specifically a high-speed and wide-range multi-mode programmable frequency divider with a 50% duty cycle. Background technique [0002] High-performance programmable frequency dividers are widely used in radio frequency and high-speed digital integrated circuits. High operating frequency, wide frequency division ratio range, low power consumption, large drive capacity, etc. are usually the general requirements of the system for frequency dividers. In July 2000, the article "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology" published on pages 1039 to 1045 of IEEE "Journal of Solid-State Circuits" (JSSC), disclosed a high-speed low-power Programmable frequency divider circuit structure with wide frequency division ratio range. How...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is: the pulse width of the output signal of the existing programmable frequency divider is affected by the frequency of the input signal. With the increase of the frequency division ratio, the duty cycle decreases sharply, and the driving ability is limited; Some improved frequency dividers have complex structures and high power consumption

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