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Electrostatic discharge protecting circuit

An electrostatic discharge protection and electrostatic discharge technology, applied in the circuit field, can solve the problems of mutual influence of power supply, inability to achieve protection effect, failure of independent operation of power supply, etc., and achieve the effect of safe and simple design

Inactive Publication Date: 2012-05-30
天津南大强芯半导体芯片设计有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For mixed voltage power supply systems with variable voltage, especially a certain power terminal may be higher than VSS or lower than VSS in the application (such as external terminal 1 = 5V, external terminal 2 = 0V, external terminal 3 is a hybrid Voltage, the highest voltage range is 5V, the lowest is less than 0V), for this type of hybrid multi-power supply, there is no absolute minimum potential, so the standard ESD protection unit of the above-mentioned foundry cannot achieve the protection effect
In short, in a multi-power supply circuit system, especially in a circuit with a mixed voltage power supply, using the standard ESD unit of the foundry is prone to the problem of mutual influence between the power supplies, resulting in the failure of the independent operation of each power supply

Method used

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Examples

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Embodiment 1

[0024] Embodiment 1: a kind of electrostatic discharge protection circuit (see figure 2 ), including the I / O terminal 12 to be protected, characterized in that it also includes a power supply electrostatic discharge bus terminal 11 and an electrostatic discharge protection assembly; wherein said electrostatic discharge protection assembly includes a transistor, one end of which is connected to the power supply electrostatic discharge bus terminal 11 , and the other end is connected to the I / O terminal 12 to be protected.

[0025] The above-mentioned electrostatic discharge bus terminal of the power supply is the positive power supply terminal 1, the I / O terminal to be protected is the grounding power supply terminal 2, and the transistor is two low-voltage N-type semiconductors 7; the two low-voltage N-type semiconductors 7 are connected in series , and each low-voltage N-type semiconductor 7 adopts a diode connection; the drain of said one low-voltage N-type semiconductor 7 ...

Embodiment 2

[0026] Embodiment 2: a kind of electrostatic discharge protection circuit (see figure 2 ), including the I / O terminal 12 to be protected, characterized in that it also includes a power supply electrostatic discharge bus terminal 11 and an electrostatic discharge protection assembly; wherein said electrostatic discharge protection assembly includes a transistor, one end of which is connected to the power supply electrostatic discharge bus terminal 11 , and the other end is connected to the I / O terminal 12 to be protected.

[0027] The above-mentioned power electrostatic discharge bus terminal is a hybrid voltage power supply terminal 10, the I / O terminal to be protected is a ground power supply terminal 2, and the transistor is a high-voltage P-type semiconductor HVPMOS tube 4; said high-voltage P-type semiconductor HVPMOS tube Both the gate and the substrate of 4 are connected to the highest potential, that is, the positive power supply terminal 1, the source of the high-volt...

Embodiment 3

[0028] Embodiment 3: a kind of electrostatic discharge protection circuit (see figure 2 ), including the I / O terminal 12 to be protected, characterized in that it also includes a power supply electrostatic discharge bus terminal 11 and an electrostatic discharge protection assembly; wherein said electrostatic discharge protection assembly includes a transistor, one end of which is connected to the power supply electrostatic discharge bus terminal 11 , and the other end is connected to the I / O terminal 12 to be protected.

[0029] The electrostatic discharge bus terminal of the power supply mentioned above is the positive power supply terminal 1, the I / O terminal to be protected is the hybrid voltage power supply terminal 10, and the electrostatic discharge protection component is a combination of three sets of high-voltage NMOS tubes HVNMOS tube 5 and resistor 6; Each group of high-voltage NMOS transistors HVNMOS transistors 5 and resistors 6 are connected in series with each...

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Abstract

The invention relates to a static-discharge protection circuit, which comprises an I / O terminal to be protected and is characterized in that a power supply static-discharge bus terminal and a static-discharge protection component are also included, wherein, the static-discharge protection component comprises a transistor, one end of which is connected with the power supply static-discharge bus terminal and the other end is connected with the I / O terminal to be protected. The static-discharge protection circuit has the advantages as follows: (1) the situations that power supplies influence each other cannot occur no matter when in static-discharge or in normal operation by applying a provided static-discharge protection network configuration in a circuit with multiple power supplies and different voltages; (2) a low-voltage P-type metal oxide semiconductor is not used if a withstand voltage is requested by applying the provided static-discharge protection network configuration in the circuit with multiple power supplies and different voltages, thereby being safer and simpler in design; (3) a circuit combination composed of any two or a plurality of circuit modules can be used for protecting the circuit from static-discharge by different circuit terminals.

Description

(1) Technical field: [0001] The invention relates to a circuit, in particular to an electrostatic discharge (Electrostatic Discharge; ESD) protection circuit. (two) background technology: [0002] In recent years, semiconductor process technology has continued to develop into deep submicron technology, the feature size has become shorter, and the gate oxide layer has become thinner. The more advanced process technology of CMOS components and the smaller component size have increased the speed of circuit operation, but also increased the sensitivity of electrostatic discharge (Electrostatic Discharge ESD), which has greatly reduced the protection ability of CMOS circuits against ESD. However, the static electricity generated in the external environment has not been reduced, so the damage of the CMOS circuit due to ESD is more serious. [0003] Friction between materials generates electrostatic charges, and the formation and storage of charges can result in electrostatic volt...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02H9/00
Inventor 戴宇杰张小兴吕英杰黄维海王洪来
Owner 天津南大强芯半导体芯片设计有限公司
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