Phase-change memory

Abstract

The invention discloses a phase-change memory which comprises a plurality of memory units, a column gating circuit, a decoder, a comparative readout resistor, a sensitive amplifier, a read-write drive circuit and a row decoder; bit lines of all the memory units are connected to the column gating circuit and the decoder; the word lines of all the memory units are connected to the row decoder; the column gating circuit and the decoder are connected with the read-write drive circuit and the sensitive amplifier; the read-write drive circuit is connected with the sensitive amplifier by the comparative readout resistance; the memory unit comprises a gating diode and at least two phase-change memory units; after being parallel, the phase-change memory units are connected with the gating diode. The phase-change memory of the invention adopts a 1DnR memory unit structure, thus reducing the chip area occupied by the gating diode.

Description

technical field [0001] The invention belongs to the technical field of semiconductor storage and relates to a memory, in particular to a phase-change memory capable of accelerating the reading speed of the memory and increasing the reading margin. Background technique [0002] Phase change memory technology is based on Ovshinsky's proposal in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys. Lett., 18, 254-257, 1971) The idea that the phase change film can be applied to the phase change storage medium is established, and it is a storage device with low price and stable performance. Phase-change memory can be made on a silicon wafer substrate, and its key materials are recordable phase-change films, heating electrode materials, heat-insulating materials, and lead-out electrode materials. Including how to reduce device material and so on. The basic principle of phase change memory is to use electric pulse signal to act on the device unit, so...

AI Technical Summary

Problems solved by technology

[0006] There are many problems in the 1D1R memory with this traditional structure: First, due to the process deviation and the unequal distance between the memory cell and the drive circuit in the chip layout, the resistance value distribution of the phase change unit in the "RESET" and "SET" states is different. Wider, even the phenomenon that the resistances in the two states overlap, resulting in data storage errors

Second, because the read operation requires a pulse signal, the phase change in 1R1D will continue to decrease with the accumulation of the read pulse signal after multiple read operations. When the resistance value under "RESET" is smaller than the DUMMY resistance, Data read errors will be released, and this phenomenon will be more serious if a higher read operation voltage or a higher read operation current is used

Third, because the resistance value of the phase-change memory cell will become very complicated after multiple RESET and SET operations, and the DUMMY resistance will not change accordingly, so the comparison with the DUMMY resistance will become more difficult

[0007] From the above, it can be seen that the traditional phase-change memory has the following problems to be solved: First, under the traditional 1T1R or 1D1R structure, most of the area of ​​the memory array is consumed by the MOS transistor or diode used as the gate transistor. However, it has not reached the highest integration level of the phase change unit

Second, according to the experiment, it is found that the phase change memory cells on the same phase change memory chip, due to the lack of process consistency and the different distances between the phase change cells and the driving circuit, the distribution of high resistance values ​​after RESET operation is different from the distribution of low resistance values ​​after SET. The value distribution is very wide (high resistance 20k-500kOhm, low resistance 1k-10kOhm), and even high resistance and low resistance values ​​overlap, which has a great impact on the correct reading of the data on the phase change unit, and the resistance of the circuit The interference ability is weak, and the reading speed is slow; thirdly, the phase change memory depends on Joule heat to change its resistance state. The resistance of the SET state will decrease as the number of read operations increases. Under the traditional 1T1R and 1D1R structures, when the resistance value of the phase change unit in the "RESET" state is low to a certain extent, reading errors may occur, and high and low resistance The smaller the value gap will also affect the chip read margin

Fourth, after the phase change unit is operated by multiple RESET or SET, the resistance value of the device itself will be very complicated

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