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Image recognition accelerator and MPU chip possessing image recognition accelerator

A technology of image recognition and acceleration devices, which is applied in the direction of processor architecture/configuration, machine execution devices, character and pattern recognition, etc. It can solve the problems of narrow effective field of acceleration circuits, large differences in parameters and steps, etc.

Inactive Publication Date: 2008-08-06
马磊
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the image recognition algorithm is aimed at different applications, the parameters and steps are often very different. Therefore, the effective field of the acceleration circuit for a specific algorithm is often very narrow; in addition, the image recognition algorithm is constantly updated and improved. Acceleration circuits for specific algorithm implementations that quickly reveal limitations over time

Method used

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  • Image recognition accelerator and MPU chip possessing image recognition accelerator
  • Image recognition accelerator and MPU chip possessing image recognition accelerator
  • Image recognition accelerator and MPU chip possessing image recognition accelerator

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Embodiment Construction

[0014] The various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings:

[0015] Fig. 1 is a block diagram of a microprocessor system according to an embodiment of the present invention. The figure describes in detail the internal system block diagram of an embedded processor chip adopting the present invention. The processor consists of a microprocessor core (101), an image recognition acceleration device (102), a system bus (103), a memory controller (104), a direct memory access controller (105), an interrupt controller (106), and a network Controller (107), video controller (108), low-speed peripheral bridge (109) for connecting low-speed peripherals, and general-purpose IO (113), I 2 C bus controller (112), UART controller (111) and SPI controller (110) are formed. The microprocessor core may be a commercial IP core such as ARM9 or ARM11. In order to meet performance requirements, the microprocessor core general...

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PUM

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Abstract

The invention provides an image recognition accelerator which mainly comprises a system bus arbitrator, an inside bus, an access control unit, a command distribution device, a direct memory access controller, a system task array, a resource statistical meter, a running task reserving station, a configuration memory, a plurality of command encoder units, a data memory, a plurality of processing unit arrays, a data reserving station and a Gray encoder. Compared with the prior special image recognition accelerating chip, the image recognition accelerator has the advantages of high performance, low cost, flexible application, etc.

Description

Technical field [0001] The present invention relates to image processing large-scale integrated circuit technology, and more specifically, to the technology of image processing acceleration devices. Background technique [0002] With the development of information and network technology, the connotation of digital content is becoming more and more abundant, from the original single text and pictures to the audio, video and 3D environment and other media, involving education, science, finance, culture, entertainment, Business, communications and other fields. In terms of technology, digital content development, digital content delivery, and digital content security are the three major supports of the digital content industry. On the one hand, digital content development is closely integrated with cultural creativity and artistic creation, but also inseparable from technologies such as images, audio, video, and Web2.0; with the development of broadband technology, digital content d...

Claims

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Application Information

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IPC IPC(8): G06K9/00G06T1/20G06F9/38
Inventor 冯一名孟路董亮
Owner 马磊
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