Booster circuit

Abstract

A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared. Thus, the boosting circuit can suppress reducing electric charge transmission efficiency, and realizing lower electric consumption and cutting down allocation area by controlling N well potential of the switching element having triple well structure.

Description

technical field [0001] The present invention relates to a voltage boosting circuit using a switching element of a triple well structure. Background technique [0002] In recent years, in flash memory (flash memory), which is a kind of nonvolatile semiconductor storage device, data reading and data rewriting under a single power supply voltage or a low power supply voltage are required, and when each operation is performed, a A boost circuit that provides a positive or negative boost voltage is required. Also, even in the CMOS process, the power supply voltage generated by the booster circuit is used to improve the characteristics of the analog circuit. [0003] Conventionally, a booster circuit using a switching element with a triple well structure is known (refer to the specifications of US Pat. Nos. 6,100,557, 6,121,821, and 7,102,422). [0004] Fig. 25 shows an example of a conventional booster circuit. In FIG. 25 , 901 is a booster circuit that receives two-phase cloc...

AI Technical Summary

Problems solved by technology

[0010] However, since the above-mentioned conventional boost circuit 901 connects the source of the charge transfer transistor 906 to the N-well 908, the N-well 908 is charged with the voltage shift amplitude of the clock signals CLK1 and CLK2 according to the voltage shift of the clock signals CLK1 and CLK2. The formed parasitic capacitance is charged and discharged, and as a result, there is a problem that the current consumption increases

[0011] Furthermore, since the charge supplied by the clock signals CLK1 and CLK2 is used as charge and discharge charge of the N well 908, there is a problem that the boosting efficiency decreases.

[0012] In addition, since the source of the charge transfer transistor 906 is connected to the N well 908, the N well 908 needs to be separated between the charge transfer transistors 906, and thus, there is a problem that the layout area increases.

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