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Polymetal interconnecting layer combined aerial on chip

A technology of combining antenna and interconnect layer

Inactive Publication Date: 2008-07-23
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional dipole antennas, folded line antennas, PIFA antennas, and slot antennas generally have problems such as large antenna size, poor transmission performance, performance is easily affected by nearby metal components, and performance is easily affected by the packaging structure.
[0003] Through literature search to prior art, it is found that the on-chip antenna based on CMOS process, especially the on-chip antenna applied to wireless interconnection is one of the research hotspots in the modern integrated circuit technology, J.Branch et al published in February 2005 in The second issue of IEEE Electron Device Letters: Wireless Communication in a Flip-Chip Package using Integrated Antennas on Silicon Substrate, proposed the use of on-chip thin wire couplers However, due to the limitation of the performance of the on-chip antenna, the communication transmission loss of this system is very large and the efficiency is low; T.Kikkawa et al. published in October 2005 in the Electronic Devices Letters of the Institute of Electrical and Electronics Engineering (IEEE The tenth issue of Electron Device Letters: Ultrawideband Characteristics of Fractal Dipole Antennas Integrated on Si for ULSI Wireless Interconnects (Ultrawideband Characteristics of Fractal Dipole Antennas Integrated on Si for ULSI Wireless Interconnects). pole antenna for ultra-broadband wireless interconnection, but the antenna is large in size and occupies a large amount of valuable chip area, so it is not practical; K. Ohashi et al. published it in the Japanese Journal of Applied Physics in April 2007 Applied Physics) article: On-chip Yagi-Uda Antenna for Horizontal Wireless Signal Transmission in Stacked Multi Chip Packaging (On-chip Yagi-Uda Antenna for Horizontal Wireless Signal Transmission in Stacked Multi Chip Packaging), proposed an on-chip Yagi-Uda antenna, obtained Higher transmission gain, however, the size of the antenna is too large to be practically applied to on-chip wireless interconnection

Method used

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Embodiment Construction

[0016] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings: this embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following the described embodiment.

[0017] As shown in FIG. 1 , this embodiment includes: a multi-metal interconnection layer radiating element 1 , a feed through hole 2 , a short circuit through hole 3 , a silicon dioxide layer 4 and a silicon substrate 5 . The silicon substrate 5 is located at the bottom, the silicon dioxide layer 4 is above it, and the multi-metal interconnection layer radiation element 1 , feed through hole 2 and short circuit through hole 3 are above it. The center of the multi-metal interconnection layer radiating element 1 is connected to the feed through hole 2 , and both ends a...

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Abstract

The invention relates to an assembly antenna with on-chip polymetallic interlocking layer belonging to the technology field of integrated circuits, which comprises a polymetallic interlocking layer radiating element, a feed perforation, a short-circuiting perforation, a silica dioxide layer and a silicon chip, wherein the center of the polymetallic interlocking layer radiating element is connected with the feed perforation, and the two ends of the polymetallic interlocking layer radiating element are connected with the short-circuiting perforation, thereby forming the polymetallic interlocking layer assembly antenna. Due to adopting the polymetallic interlocking layer composite structure, the invention is capable of effectively increasing radiation volume of the on-chip antenna, reducing the measurement of the on-chip antenna, increasing impedance bandwidth of the on-chip antenna, notability improving transmission gain of the on-chip antenna for applying wireless interconnection, and not occupying any additional chip area, otherwise, the invention is totally compatible for main flow CMOS technology, is fit for the silicon chip with miscellaneous specific resistance without additional impedance match components, at the same time is fit for multilayer low-temperature co-melting ceramic technology, and which has extensive technology adaptability.

Description

technical field [0001] The invention relates to an antenna in the technical field of integrated circuits, in particular to an on-chip multi-metal interconnection layer combined antenna. Background technique [0002] With the continuous development of microelectronics technology, the scale of integrated circuit components increases geometrically as described by Moore's law. Recently, with the maturity and application of micron and submicron technology, people pay more and more attention to the signal integrity of interconnection, that is, global interconnection transmission delay, interconnection power consumption and interconnection reliability. Based on the above considerations, many scholars have proposed to replace the existing interconnection system with wireless interconnection, that is, using on-chip integrated antenna, power amplifier (PA), low noise amplifier (LNA), codec (Coder / Decoder) And other components of the wireless transceiver system to achieve functions su...

Claims

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Application Information

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IPC IPC(8): H01Q1/38H01Q21/00H01Q21/30
Inventor 吴琦金荣洪耿军平叶声毛军发
Owner SHANGHAI JIAO TONG UNIV
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