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High speed deposition micro crystal silicon solar battery P/I interface processing method

A technology of solar cells and processing methods, which is applied to circuits, electrical components, sustainable manufacturing/processing, etc., can solve the problems of increasing the P/I interface defect state and the thickness of the amorphous incubation layer, so as to improve battery efficiency and reduce interface state, reducing the effect of the incubation layer

Inactive Publication Date: 2008-04-09
NANKAI UNIV
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  • Description
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Problems solved by technology

[0005] The purpose of the present invention is to provide a method for processing the P / I interface of microcrystalline silicon solar cells that can improve the efficiency of high-speed deposition of microcrystalline silicon cells. P / I Interface Defect States and Thickness of Amorphous Incubation Layer

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  • High speed deposition micro crystal silicon solar battery P/I interface processing method

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Embodiment 1

[0025] Embodiment 1, the preferred implementation conditions of the present invention are as follows: the substrate is placed in the reaction chamber, the air pressure in the reaction chamber is maintained at 1.6 torr, and the electrode distance is 12 mm. Power on to start deposition, first set the glow power to 25W, the silane concentration to 3%, the first deposition rate under this condition is about 3 / s, keep the first deposition rate for 5 minutes and 30 seconds, and form the first intrinsic microcrystalline silicon thin film layer with low defect and high crystallization of about 100nm; 50W, silane concentration is 5%, the second deposition rate under this condition is about 8.5 / s, maintain the second deposition rate for 27 minutes, and form a second intrinsic microcrystalline silicon film layer of about 1400 nm. It can be seen from Fig. 2 that the cell efficiency with the low-velocity interface layer with 100nm low defect and high crystallization is increased by ab...

Embodiment 2

[0026] Embodiment 2, if only using the second deposition rate to deposit the intrinsic microcrystalline silicon thin film, the corresponding intrinsic microcrystalline silicon thin film layer thickness in Figure 2 is 0nm, that is, the implementation conditions without the low-speed intrinsic microcrystalline silicon thin film layer are as follows: The substrate was placed in the reaction chamber, the air pressure in the reaction chamber was kept at 1.6 torr, and the electrode distance was 12 mm. The glow power is set to 50W, the silane concentration is 5%, and the deposition rate under these conditions is about 8.5 / s, keep the deposition rate for 29 minutes (time), and form an intrinsic microcrystalline silicon thin film layer of about 1500 nm (thickness). It can be seen from Figure 2 that the cell efficiency without the low-speed intrinsic microcrystalline silicon thin film layer is the lowest relative to the cell efficiency with the low-speed intrinsic microcrystalline sil...

Embodiment 3

[0027] Embodiment 3, if the thickness of the first intrinsic microcrystalline silicon film deposited by the first deposition rate is thicker, the implementation conditions are as follows: the substrate is placed in the reaction chamber, the air pressure in the reaction chamber is maintained at 1.6torr, and the electrode The distance is 12mm. Power on to start deposition, first set the glow power to 25W, the silane concentration to 3%, the first deposition rate under this condition is about 3 / s, the first deposition rate is maintained for 11 minutes, and a first intrinsic microcrystalline silicon thin film layer with a thickness of about 200 nm and low defects and high crystallization is formed. Then when other process conditions remain unchanged, only the glow power is changed to 50W, the silane concentration is 5%, and the second deposition rate under this condition is about 8.5 / s, maintain the second deposition rate for 25 minutes, and form a second intrinsic microcryst...

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Abstract

The invention discloses a high-speed deposition method on a P / I interface of a microcrystal silicon solar battery, which comprises controlling glowing power and silicane concentration by ultra-high frequency plasma enhanced chemical vapor deposition method and depositing a first intrinsic microcrystal silicon film layer on a P player with a first deposition rate; adjusting glowing power and silicane concentration without extinguishment of plasma glow and growing a second intrinsic microcrystal silicon film layer on the first intrinsic microcrystal silicon film layer with a second deposition rate, wherein the first deposition rate is smaller than the second deposition rate. The invention uses lower glower power and lower silicane concentration to depose on P layer with smaller deposition rate to obtain high crystallized intrinsic microcrystal silicon film layer with low defect, so as to improve battery efficiency.

Description

【Technical field】 [0001] The invention relates to a silicon-based thin-film solar cell preparation process, in particular to a method for treating the P / I interface of a microcrystalline silicon solar cell that helps to improve the efficiency of high-speed deposition of a microcrystalline silicon solar cell. 【Background technique】 [0002] Among silicon-based thin-film solar cells, microcrystalline silicon (μc-Si:H) thin-film solar cells are favored by the photovoltaic industry because of their high conversion efficiency and high stability. Microcrystalline silicon (μc-Si:H) is an indirect bandgap semiconductor material with an optical bandgap of about 1.1eV. In order to fully absorb sunlight, the film thickness must be greater than 1μm. Therefore, increasing the growth rate is very important for reducing the production cost of microcrystalline silicon thin film photovoltaic cells. [0003] Many research results show that ultra-high frequency plasma-enhanced chemical vapor ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/18
CPCY02P70/50
Inventor 耿新华韩晓艳张晓丹赵颖侯国付魏长春孙健张德坤
Owner NANKAI UNIV
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