A dual-mode frequency divider

Abstract

The invention discloses a double-mode frequency divider, which comprises the following parts: double-mode frequency predivider, which divides frequency for high-frequency signal input by exterior to output the frequency dividing signal to programmable counter; programmable counter, which counts the input frequency dividing signal to generate output metering signal to signal selector at the first signal output end when the counter reaches N or generate output metering signal to signal selector at the second signal output end when the counter reaches M; signal selector, which gates the first or second signal output ends of programmable counter under mode control signal to continuously invert the condition of output end acted by clock to output the mode control signal. The invention realizes the function of programming frequency division, which elevates the working speed of circuit and simplifies the circuit structure.

Description

technical field [0001] The invention relates to the field of electronic technology, can be applied to a phase-locked frequency synthesizer in a radio frequency transceiver, and in particular relates to a frequency divider which uses a single counter to realize dual-mode frequency division. Background technique [0002] The phase-locked frequency synthesizer plays an important role in synchronization, frequency conversion and channel switching in the communication system, and is one of the indispensable components of modern communication. As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a phase-locked frequency synthesizer. The phase-locked frequency synthesizer consists of a phase-frequency detector and a charge pump (PFD / CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a programmable frequency divider. [0003] Among them, the frequency and phase detector and the charge pump are a phase comparison device. It compares the phase of the inpu...

AI Technical Summary

Problems solved by technology

[0012] The disadvantage of the dual-mode frequency divider proposed by US Patent 6,035,182 is that in a frequency division cycle, the counter needs to be programmed twice, so it needs to provide two control signals outside (in the communication system, this signal is usually generated by the baseband)

This complicates the design of the baseband of the communication system, and is also different from the common situation in which a control signal can realize frequency switching in modern communication systems

Moreover, after the control switch selects a certain signal, the counter needs to be preset. This process has a certain time delay, which reduces the working speed of the programmable frequency divider.

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