Semiconductor device and its making method

Abstract

The present invention provides a strain enhanced semiconductor device using amorphous carbon films and fabrication methods of forming the same. The semiconductor device includes: a semiconductor substrate with a PMOS region and a NMOS region; a first gate structure and a second gate structure; a source-electrode / drain-electrode; a siliconization region; an amorphous carbon film with tensile stress; and a dielectric layer. The amorphous carbon film, such as fluorinated amorphous carbon, is formed of a tensile film or a compressive film to act a stress capping film on the pMOS device region or the nMOS device region. The amorphous carbon film also acts a contact etching stop layer during a contact hole etching process. The problem generated by traditional using epitaxial layer SiGe and stress covering layer is avoided by fabricating strain enhanced CMOS component with amorphous carbon film.

Description

technical field [0001] The invention relates to a manufacturing method of a CMOS (Complementary Metal Oxide Semiconductor) device in an integrated circuit, in particular to a strain-enhanced CMOS device using an amorphous carbon film and a manufacturing method thereof. Background technique [0002] The main factor affecting the performance of field effect transistors is the mobility of carriers, wherein the mobility of carriers will affect the amount of current in the channel. The reduction in carrier mobility in field effect transistors not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. In the development of CMOS field effect transistors, effectively improving the mobility of carriers has always been a key item in the design of transistor structures. The problem encountered by CMOS is that the pressure sources required to improve the carrier mobility of NMOS and PMOS devices are different. [0003] In ...

AI Technical Summary

Problems solved by technology

However Si 3 N 4 For high dielectric constant materials, it will generate capacitive coupling noise between adjacent voltage transients (capacitive coupling noise)

Since the contact hole etch stop layer is close to the gate oxide layer and Si 3 N 4 Thin film, so transistor performance, such as hot carrier lifetime and negative bias temperature instability, etc., will be greatly degraded

In addition to the above-mentioned problems arising in the etching process for forming the contact hole, the compressive stress film Si 3 N 4 and tensile stress film Si 3 N 4 Has a different etch rate, so more silicide and oxide losses are generated during the etching process to form the contact hole, causing serious leakage current

Images