Embedded heterogeneous polynuclear cache coherence method based on bus snooping

Abstract

This invention discloses one imbed abnormal multi-nuclear buffer accordance method based on bus detection, which is based on one time strategy processor one degree high speed buffer accordance with main function to keep same data in multi-nuclear local one degree high speed buffer and sharing two degree high speed buffer multiple copy accordance. This invention is suitable for abnormal multi-nuclear system processor based on bus to combine two strategies advantages.

Description

technical field [0001] The invention relates to the field of heterogeneous multi-core processor systems, in particular to an embedded heterogeneous multi-core cache consistency method based on bus snooping. Background technique [0002] Multi-core processor, that is, single-chip multi-processor refers to the integration of multiple microprocessor cores on one chip, which can execute program codes in parallel, reduce the power consumption of the processor without increasing the operating frequency of the processor, and obtain high polymerization performance. The heterogeneous multi-core processor means that the multiple microprocessor cores integrated on the chip are heterogeneous. [0003] 2006 is the year with the fastest processor replacement since computer history. Processor manufacturers represented by Intel and AMD released dual-core processors at the beginning of the year, and then released a variety of dual-core processors. At the end of 2006, they released Quad-cor...

AI Technical Summary

Problems solved by technology

In this multi-core processor system, the cache structure brings new problems: if processes in different processor cores need to share some data, then there may be multiple copies of the same data stored in each L1 cache In , when the data in a certain L1 cache is updated, and the copy of the same data in other L1 caches is not modified accordingly, what those processor cores read from the private L1 cache will be "Dirty" data, resulting in the coexistence of multiple versions of the same data

In addition, after the data in a certain level-1 cache is updated, before it is written back to the level-2 cache, the data in the level-1 cache and the level-2 cache will also be inconsistent.

If there is exactly one processor core process at this time (assuming that there is no copy of the modified data in the private L1 cache of the processor core) that needs this data, when reading the L2 cache data, it will cause a data error

[0007] 2. Inconsistencies caused by process migration

[0008] 3. Data inconsistency caused by input and output operations

Assuming that there are data copies of the same data block in the second-level cache in multiple first-level caches, when the system starts an I / O operation, the I / O processor (channel DMA) may update the data in the second-level cache. data, resulting in inconsistency between the first-level cache and the second-level cache data

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