Semiconductor memory device with reduced data access time

Abstract

A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

Description

FIELD OF THE INVENTION[0001]The present invention relates to a semiconductor memory device; and, more particularly, to the semiconductor memory device capable of providing a reduced data access time.DESCRIPTION OF RELATED ART[0002]Generally, a semiconductor memory device is classified as a random access memory (RAM) and a read only memory (ROM).[0003]The RAM includes a Dynamic RAM (DRAM) and a Static RAM (SRAM). One cell of the dynamic RAM has one transistor and one capacitor and that of the static RAM does four transistors and two load resistances. The DRAM is used more widespread than the SRAM because the DRAM is more efficient than SRAM in a chip integration and a manufacturing process.[0004]Today, an operation speed of a central processing unit (CPU) is more dramatically advanced than that of the DRAM. As a result, many problems may arise because the operation speed of the memory device is slower than that of CPU. For overcoming these problems, several kinds of scheme in the mem...

AI Technical Summary

Benefits of technology

The present invention provides a memory device with high-speed data access and restoration of data access time after a data access pattern. The memory device includes a cell area with multiple unit cell blocks, each having a local bit line sense amplifier block and a global bit line sense amplifier block. A control unit generates control signals to selectively connect the global bit line sense amplifier block to either the first or second local bit line sense amplifier block based on the data access pattern. The memory device can access data in a first cell block and restore the data in a second cell block without affecting the data access time. The invention also provides a method for operating the memory device with first and second cell blocks, each having a number of cell units.

Problems solved by technology

As a result, many problems may arise because the operation speed of the memory device is slower than that of CPU.

Furthermore, since a small amount of charges stored in the capacitor may be lost with lapse of time, the memory device needs a refresh operation for periodically recharging the capacitor.

As a result, if the charge stored in the capacitor is not amplified periodically, the charge stored in the capacitor may be lost to thereby allow the stored data to be corrupted.

However, as mentioned above, it is difficult to apply the bank interleaving mode in the intra bank data access of the conventional memory device and, to obtain higher data access time in the convention memory device.

If a system uses the conventional memory device whose data access speed is seriously affected by the data access pattern, there may be occurred some critical problems about the operation reliability of the system because the operation speed of the system may not be stable.

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