Three dimensional memory device

Abstract

A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.

Description

BACKGROUND[0001]Technical Field[0002]The disclosure in generally relates to a memory device, and more particularly to a three dimensional (3D) memory device.[0003]Description of the Related Art[0004]Non-volatile memory (NVM) which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widely adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc. Recently, various three dimensional (3D) memory devices, such as a 3D flash memory device having a single gate, a double gate or a surrounding gate, has been provided in order to accommodate the rising demand for superior memory.[0005]A typical 3D memory device includes a 3D memory cell array having vertical channels formed in a multi-layer stacks. To take a single-gate vertical channel (SGVC) NAND device for example, a plurality of stacked poly-silicon conductive stripes are applied to...

AI Technical Summary

Benefits of technology

The patent text describes a way to make 3D memory devices with fewer word lines and contacts, which reduces their size and allows for higher memory densities without compromising the manufacturing process. This results in a reduction of production costs and improved yield.

Problems solved by technology

However, the word lines contacts occupy the areas of the SGVC NAND device, and the space over the memory cell array for arranging the word lines is rather limited to allow additional word lines passing there through.

But, the process window and the yield for fabrication the SGVC NAND device may be decreased, and oxide breakdown may occur due to the shrunk pitch of the word lines.

The production cost thereof may be thus increased.

In contrast, increasing the physical size of the SGVC NAND device does not meet the current trend of being lightweight and compact in memory device.

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