Dynamic random access memory device

Abstract

A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs. When the first sub word line may be selected, a predetermined voltage may be applied to the plurality of dummy bit lines for a first predetermined period in which a charge sharing operation is performed on the plurality of first memory cells connected to the selected one of the plurality of first sub word lines.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0168152, filed on Dec. 8, 2017, in the Korean Intellectual Property Office (KIPO), the content of which is hereby incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]The present inventive concept relates generally to semiconductor memory devices and, more particularly, to dynamic random access memory devices.2. Discussion of Related Art[0003]Dynamic random access memory (DRAM) devices may have an open bit line architecture or a folded bit line architecture according to an arrangement of bit lines.[0004]A DRAM device having an open bit line architecture may include a plurality of memory cell array blocks arranged in a bit line direction. In a plurality of memory cell array blocks extending in a bit line direction, those memory cell array blocks disposed at the ends thereof may include dummy bit lin...

AI Technical Summary

Benefits of technology

The present invention relates to a dynamic random access memory (DRAM) device that can prevent operational failures caused by leakage current in dummy bit lines.

Problems solved by technology

Accordingly, when a charge sharing operation is performed between a capacitor of each of the memory cells connected to the selected word line and a corresponding bit line, the access transistor may not be completely turned on, which may result in an operation failure.

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